Dynamic Voltage Scaling for SSD Power Loss Data Backup

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Solution Overview

Problem

Enterprise SSDs face challenges in reducing the cost and reliability of backup capacitors used for sudden power-off scenarios, as they require high energy capacity, which is often expensive and limited in reliability.

Innovation Solution

A low-power algorithm that dynamically reduces the supply voltage during power loss, allowing data to be written to NAND Flash using a reduced voltage, potentially supplied by a smaller and more cost-effective capacitor, such as a tantalum capacitor, while optimizing bits-per-cell and voltage scaling to minimize energy consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a large-capacity backup capacitor is used to supply energy for writing DRAM buffer to NAND Flash during sudden power-off, then the energy capacity is sufficient, but the cost increases and reliability is limited

Engineering Contradiction:
Improveenergy capacityVSAvoidcapacitor reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the voltage parameter dynamically by detecting power loss and temporarily reducing the supply voltage to the NVM from normal operating voltage to a reduced voltage level. This voltage reduction significantly decreases the energy consumption during the write operation, allowing a smaller capacitor with lower energy capacity to suffice, thereby improving reliability and reducing cost while maintaining sufficient energy supply during power-off events

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If the supply voltage is reduced temporarily during power loss, then the energy consumption is reduced, but the programming speed decreases

Engineering Contradiction:
Improveenergy consumptionVSAvoidprogramming speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent implements dynamic voltage adjustment by detecting power loss conditions and temporarily switching to a reduced voltage mode only during the critical write operation window. After the write operation completes successfully, the system returns to normal voltage operation. This dynamic approach accepts temporary speed reduction only when necessary (during power loss events) while maintaining high performance during normal operation, achieving an optimal balance between energy savings and programming speed

Inventive Principle:
Principle #15Dynamics

3Volume of stationary object

If a tantalum capacitor is used instead of other types, then the capacitance per volume is higher and weight is lower, but the cost is more expensive

Engineering Contradiction:
Improvecapacitor volumeVSAvoidmanufacturing cost
Core Design Contradiction:
Volume of stationary objectVSEase of manufacture

Solution Approach 1:

By implementing voltage reduction during power loss events, the patent decreases the total energy capacity requirement of the backup capacitor. This parameter change in energy requirement allows the system to use a smaller capacitor with lower capacitance value, making cost-effective alternatives like aluminum electrolytic capacitors viable replacements for expensive tantalum capacitors, thus reducing manufacturing cost while still providing sufficient backup energy

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the energy required for programming by up to 52%, potentially eliminating the need for large backup capacitors and extending the lifespan of the SSD capacitor, while maintaining reliability and reducing costs.

Implementation Method 1

The capacity of the backup capacitor is dictated by the energy required to back up the DRAM to the NAND Flash

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

temporarily reducing a supply voltage to the NVM; writing data to the NVM using the reduced supply voltage

Methodology Applied
Scientific EffectElectrical energy reduction through voltage scaling:

Data Source

PatentUS10726879B2Low-power data transfer from buffer to flash memory
Publication Date: 2020.07.28 SAMSUNG ELECTRONICS CO LTD
  • US10726879B2 patent drawing
  • US10726879B2 patent drawing
  • US10726879B2 patent drawing

AI summary

A solid-state drive (SSD) may include a volatile buffer such as DRAM, a non-volatile memory (NVM) such as NAND Flash connected to the volatile buffer, and a capacitor connected to both, where the capacitor may have an energy capacity insufficient to supply the buffer and NVM using a normal supply voltage in a normal mode, but sufficient to supply the buffer and NVM using at least one reduced supply voltage in a temporary mode; and a related method may include programming data to the NVM by temporarily reducing the supply voltage to the NVM, and writing data to the NVM using the reduced supply voltage.