SSD Write Buffer Early Deallocation for Higher Throughput

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Solution Overview

Problem

The delay in write buffer deallocation in solid state drives (SSDs) due to time-consuming data programming operations leads to reduced system throughput and increased buffer memory requirements.

Innovation Solution

Implementing an early de-allocation method for the write buffer after data is stored in a temporary register, but before actual programming into non-volatile memory units, with mechanisms for data recovery to mitigate potential loss, such as using additional non-volatile memory or error-correcting codes like Reed-Solomon coding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the write buffer is deallocated only after successful data programming to non-volatile memory, then data reliability is ensured, but system throughput is reduced and buffer memory requirements increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by deallocating the write buffer early after data is transferred to the temporary register, before the actual programming to non-volatile memory completes. This early deallocation improves throughput while maintaining reliability through subsequent verification steps that confirm successful programming after buffer release.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the write buffer is deallocated only after successful data programming to non-volatile memory, then data reliability is ensured, but buffer memory requirements increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidbuffer memory requirements
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by deallocating the write buffer early after data is transferred to the temporary register, before the actual programming to non-volatile memory completes. This early deallocation reduces buffer memory requirements while maintaining reliability through subsequent verification steps that confirm successful programming after buffer release.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If early de-allocation of write buffer is implemented, then system throughput is improved and buffer memory requirements are reduced, but data loss risk increases

Engineering Contradiction:
Improvesystem throughputVSAvoiddata loss risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies feedback by implementing verification mechanisms that monitor and confirm successful data programming after the write buffer has been deallocated. This feedback system detects programming status and triggers appropriate error handling only when needed, allowing early buffer release while maintaining data reliability through post-deallocation verification.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies beforehand cushioning by implementing error correction codes and verification mechanisms that are prepared in advance to handle potential programming failures. These protective measures are in place before deallocation occurs, cushioning against data loss risk while enabling early buffer release to improve throughput.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9471242B2Early de-allocation of write buffer in an SSD
Publication Date: 2016.10.18 PALISADE TECH LLP
  • US9471242B2 patent drawing
  • US9471242B2 patent drawing
  • US9471242B2 patent drawing

AI summary

A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register.