SSD Write Control Using Segmented SLC and MLC Memory Areas
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Solution Overview
Problem
Solid state storage devices with multi-level cell (MLC) non-volatile memory face performance deterioration due to slow writing speeds, which is exacerbated by the need for time-consuming garbage collection and insufficient buffering capacity during continuous write operations.
Innovation Solution
The device divides the non-volatile memory into a first area for buffering in a single-level cell (SLC) write mode and a second area for storing data in an MLC write mode, with garbage collection occurring when the first area reaches a threshold, allowing for faster write speeds and improved performance by utilizing SLC mode for initial data storage and MLC mode for subsequent data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC write mode is used for all data storage, then storage capacity is maximized, but write speed deteriorates
Solution Approach 1:
The non-volatile memory is divided into two distinct areas: a first area operating in SLC mode for fast write operations and a second area operating in MLC mode for high-capacity storage. This segmentation allows the system to simultaneously achieve both high write speeds and high storage capacity by routing different data to appropriate areas.
Solution Approach 2:
Different regions of the non-volatile memory are assigned different operational modes with different characteristics. The first area is optimized for speed (SLC mode) while the second area is optimized for capacity (MLC mode), allowing each local region to perform its specialized function effectively.
2Productivity
If garbage collection is performed frequently to maintain performance, then write performance is maintained, but loss of time increases
Solution Approach 1:
The system performs preliminary actions by proactively managing the first area before it becomes completely full. The controller monitors the fill level of the first area and initiates garbage collection or data migration to the second area before performance degradation occurs, preventing rather than reacting to performance issues.
Solution Approach 2:
The first area acts as an intermediary buffer between the host and the second area. It absorbs write operations at high speed temporarily, then gradually migrates data to the second area during low-activity periods, mediating between the need for fast writes and the need for garbage collection.
3Productivity
If first area size is increased to improve buffering capacity, then write performance improves, but storage capacity is reduced
Solution Approach 1:
The controller dynamically manages the first and second areas, adjusting data migration timing and rates based on system conditions. The first area size is optimized for performance while the second area provides bulk capacity, with dynamic data movement between them based on workload patterns and fill levels.
Data Source
AI summary
A solid state storage device includes a control circuit, a volatile memory and a non-volatile memory. The non-volatile memory is divided into a first area and a second area. After the host issues a write command and a write data, the control circuit monitors a data amount of the write data continuously stored into the non-volatile memory. Before the data amount of the write data continuously stored into the non-volatile memory reaches a predetermined amount, the write data is stored into plural buffering blocks of the first area in a first write mode. After the data amount of the write data continuously stored into the non-volatile memory reaches the predetermined amount, the write data is stored into plural storing blocks of the second area in a second write mode.