SSD Memory Write Timing Using Dummy Data and Data Strobe
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Solution Overview
Problem
The distortion of data strobe signal waveforms during transmission in solid state drives (SSDs) can cause incorrect data fetching by nonvolatile memory, particularly due to timing deviations and power supply voltage fluctuations, leading to inefficiencies in data transfer.
Innovation Solution
The implementation of a memory system where a memory controller transmits dummy data on signal lines before and after the data strobe signal to stabilize the power supply voltage and adjust signal timings, ensuring synchronized data transfer with the data strobe signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data strobe signal is transmitted without dummy data, then transmission speed is faster, but waveform distortion and timing deviation occur causing incorrect data fetching
Solution Approach 1:
Dummy data is transmitted before the actual data to preliminarily activate the signal lines and stabilize the power supply voltage. This preliminary action ensures that when the actual data is transmitted, the signal lines are already in a stable state, preventing waveform distortion and timing deviation without significantly impacting the overall data transfer time.
2Reliability
If dummy data is transmitted to stabilize power supply voltage, then data fetching accuracy improves, but device complexity increases
Solution Approach 1:
The dummy data transmission serves a dual purpose: it acts as both valid data transmission (maintaining protocol simplicity) and as a power supply stabilization mechanism. By using ordinary data transmissions for this stabilizing function, no additional dedicated stabilization circuitry or complex control mechanisms are needed, keeping the device complexity low while improving data fetching accuracy.
Data Source
AI summary
A memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller is configured to: after transmitting a write command and an address to the nonvolatile memory via a first signal line, transmit dummy data to the nonvolatile memory via the first signal line during at least a portion of a period that is between when the address is transmitted via the first signal line and when write data of the write command is transmitted via the first signal line, and after transmitting the dummy data via the first signal line, transmit a data strobe signal to the nonvolatile memory via a second signal line and transmit the write data of the write command to the nonvolatile memory via the first signal line in synchronization with the data strobe signal.