SSF Receiver Front End for 14 Gbps ISI Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed serial data links in DRAM-GPU interfaces face challenges with inter-symbol interference (ISI) due to frequency-dependent losses, and current solutions using folded-cascode amplifiers limit bandwidth and increase power consumption, requiring additional amplification stages that impact low-frequency linearity.
Innovation Solution
A super source follower (SSF) amplifier with transistors of relative sizes selected to provide a frequency response peak at approximately ⅔ of the data rate is used in the analog front end, allowing direct driving of a non-linear equalizer without the need for secondary amplification stages, thereby reducing power consumption and extending bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a folded-cascode amplifier is used to convert single-ended data stream, then the amplifier can perform voltage level conversion, but it introduces an extra pole that limits the bandwidth of CTLE
Solution Approach 1:
The patent changes the amplifier topology from folded-cascode to super source follower, and adjusts transistor size ratios (e.g., W/L ratios of M1 and M2) to optimize the frequency response. This parameter change eliminates the bandwidth-limiting pole while maintaining voltage level conversion capability, achieving both wide bandwidth and low power consumption.
2Device complexity
If folded-cascode amplifier directly drives the DFE, then the structure is simplified, but the bandwidth is limited due to the extra pole
Solution Approach 1:
The patent changes the amplifier topology to super source follower configuration, which fundamentally alters the frequency response characteristics by eliminating the dominant pole present in folded-cascode amplifiers. This allows direct driving of DFE with adequate bandwidth while keeping the structure relatively simple.
3Speed
If second stage amplifiers are added to compensate for bandwidth limitation, then the bandwidth requirement is met, but power consumption increases and low-frequency linearity deteriorates
Solution Approach 1:
The patent changes the fundamental amplifier topology to super source follower, which inherently provides wide bandwidth without requiring additional amplification stages. This single-stage solution reduces power consumption compared to multi-stage architectures while maintaining the bandwidth needed for high-speed operation.
4Speed
If second stage amplifiers are added to meet bandwidth requirements, then the bandwidth is sufficient, but low-frequency linearity is degraded
Solution Approach 1:
The patent changes the amplifier topology to super source follower, which provides inherently better low-frequency linearity compared to folded-cascode amplifiers. The modified structure maintains adequate bandwidth for high-speed operation while preserving linearity characteristics crucial for accurate signal reconstruction.
Data Source
AI summary
A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ⅔ of the data rate.