Source Synchronous Interface DFT for At-Speed Fault Coverage

The patent segments the testing process into two distinct phases: (1) test vector application phase using slow DFT clocks for scanning test vectors into the device under test, and (2) at-speed verification phase using fast functional clocks to propagate and capture test vectors through the actual functional paths. This segmentation allows each phase to use the appropriate clock speed for its specific purpose, resolving the contradiction between test vector transfer capability and at-speed test coverage.

The patent implements dynamic clock switching where the clock frequency is changed based on the testing phase. The DFT clock generator can switch between slow DFT clocks during vector application and fast functional clocks during verification. This dynamic adaptation allows the system to optimize clock speed for each specific operation, enabling both easy test vector transfer and high at-speed test coverage.

The patent segments the data path into scan chain paths (using slow DFT clocks for serialization) and functional paths (using fast functional clocks for propagation). This allows scan chain operation to maintain ease of use while functional path verification achieves high efficiency through faster clocking, thereby resolving the contradiction between scan chain operation and test efficiency.

The patent enables continuous useful action by allowing test vectors to be applied through scan chains at slow speeds while simultaneously or subsequently verifying the same vectors through functional paths at full operating speeds. This continuous operation at appropriate speeds for each path type maximizes overall test efficiency while maintaining scan chain operability.