String Select Line Oxide Layer for 3D Memory Gate Control
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Solution Overview
Problem
Current three-dimensional memory cell arrays face challenges in size reduction due to limitations in photolithography technology, and the process of forming these arrays is complex, leading to difficulties in controlling individual gates in the string select line (SSL) and potential unintended programming or erasure of gates.
Innovation Solution
A method for fabricating a string select line (SSL) in a three-dimensional memory array involving a dielectric substrate with stacked dielectric and conductive layers, a hard mask layer, and a heat treatment to form an oxide layer on the sidewalls, allowing for separate fabrication of the SSL and word line, using a standard gate oxide as the gate dielectric to reduce threshold voltage and prevent unwanted programming or erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory cell array is formed using existing photolithography technology, then memory storage capacity can be increased, but size reduction is still restricted by photolithography limitations
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrays to three-dimensional structures by stacking multiple films and constructing memory cells vertically. This dimensional change allows increased storage capacity while overcoming photolithography size reduction limits, as the memory structure extends in the vertical dimension rather than relying solely on planar scaling.
2Device complexity
If the process of forming three-dimensional memory cell array is simplified, then fabrication complexity is reduced, but control of individual gates in SSL becomes difficult
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming the stacked layer structure, creating openings, depositing conductive layers, and patterning. This segmentation allows complex three-dimensional structures to be built through manageable sequential steps, maintaining fabrication control while managing overall process complexity.
Solution Approach 2:
The stacked layer structure including dielectric layers and first conductive layers is formed in advance before creating openings and adding the string select line. This preliminary formation of the memory cell array structure enables subsequent precise control of individual gates during SSL fabrication, as the foundation is already in place for targeted modifications.
3Manufacturing precision
If standard gate oxide is used as gate dielectric in SSL, then threshold voltage is reduced and gate control is improved, but fabrication process becomes more complex
Solution Approach 1:
The patent applies different dielectric materials to different regions: standard gate oxide is used specifically for the SSL gate dielectric to achieve low threshold voltage and precise control, while other regions may use different dielectric materials appropriate for their functions. This localized material selection optimizes gate control where needed without unnecessarily complicating the entire fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of gates in the SSL, reduces threshold voltage, and prevents unintended programming or erasure, simplifying the fabrication process and improving the functionality of the three-dimensional memory array.
Implementation Method 1
a heat treatment is performed to form an oxide layer on a sidewall of the portion of the stacked layer
Data Source
AI summary
The present invention further provides a string select line (SSL) of a three-dimensional memory array, including: a dielectric substrate; an SSL structure disposed on the dielectric substrate, wherein the SSL structure includes a plurality of dielectric layers and a plurality of first conductive layers, the dielectric layers and the first conductive layers stacked alternatively; a second conductive layer covering sidewalls and a top portion of the SSL structure; and an oxide layer disposed between the first conductive layers and the second conductive layer, and contacting with the first conductive layers and the second conductive layer.