Embedded SSL/TLS HMAC Data Path for Unaligned High-Throughput Transfers
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Solution Overview
Problem
Existing SSL/TLS throughput in embedded devices is inefficient due to multiple memory copies, CPU-intensive decryption, and limited data transfer capabilities of HMAC hardware, leading to slow performance and increased power consumption.
Innovation Solution
Implementing a method that avoids intermediate buffers, supports multi-input and unaligned data for HMAC hardware, and enables single request transfers to the host, enhancing SSL/TLS throughput by optimizing data flow and reducing memory copies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred through multiple intermediate buffers (scatter buffers to linear hold buffer to linear buffer), then data can be properly assembled and decrypted, but the number of memory copy operations increases and throughput decreases
Solution Approach 1:
The patent removes the intermediate linear hold buffer from the data path, extracting the inefficiency from the system. Data flows directly from TCP scatter buffers to the SSL/TLS linear buffer, eliminating one complete memory copy operation while maintaining data integrity through proper buffer management and alignment handling.
Solution Approach 2:
The linear buffer is designed to serve multiple purposes: it acts as both the destination for TCP data assembly and the source for HMAC computation and SSL/TLS decryption. This multi-functionality eliminates the need for separate intermediate buffers, reducing memory copies while maintaining reliable data processing.
2Device complexity
If HMAC hardware supports only one-shot input with aligned four-byte boundaries, then hardware implementation is simpler, but data transfer flexibility is reduced and additional buffering is required
Solution Approach 1:
The HMAC hardware was redesigned with dynamic capabilities to accept data in multiple transfers rather than requiring a single static input. The hardware now includes state machine logic that can accumulate data across multiple transfers, handle unaligned boundaries, and maintain proper alignment internally while accepting flexible external inputs.
Solution Approach 2:
The data input to HMAC is segmented into multiple transfers rather than requiring a single complete input. The hardware processes data in segments, accumulating it in an internal buffer until sufficient data is available for aligned processing, allowing flexible data source accommodation without sacrificing hardware efficiency.
3Quantity of substance
If 16 KB SSL/TLS records are transferred in multiple 1460-byte chunks through scatter buffers, then host memory constraints are respected, but the number of request-response cycles increases to 12
Solution Approach 1:
The patent changes the dimension of data transfer by enabling the host to request and receive large blocks (up to 16 KB) in a single operation rather than being constrained to small chunked transfers. This dimensional change in transfer size eliminates multiple request-response cycles while the host manages the resulting large buffer allocations.
Solution Approach 2:
The host performs preliminary action by allocating large buffers in advance and issuing single large read requests, rather than repeatedly requesting small chunks. This preliminary buffer allocation and single-request approach reduces the number of interaction cycles between host and SSL/TLS layer, improving throughput.
4Reliability
If data is padded and prepended for HMAC computation, then message authentication is properly performed, but additional memory is required and data transfer complexity increases
Solution Approach 1:
The data preparation operations (prepending and padding) are merged into the existing linear buffer that already contains the SSL/TLS record data. Rather than creating separate prepared buffers, the hardware directly processes the contiguous data in the linear buffer, performing prepend and pad operations in-place or through efficient memory operations that avoid additional complex buffering.
Data Source
AI summary
An embedded system includes hash message authentication code (HMAC) hardware. The HMAC hardware receives data in separate data transfers to compute a hash. The HMAC hardware receives data of unaligned lengths in at least one of the separate data transfers. The data of unaligned lengths includes fewer valid bytes than the transfer size. The HMAC hardware responds to a residue indication indicating valid bytes associated with the data transfer to fill in the residue from a subsequent data transfer. For each data transfer the HMAC hardware receives an indication of whether the data is final data or if more data will be transferred for computation of the hash. The embedded system loads a linear buffer directly from scatter buffers, which contain encrypted data from a network. Decrypted data in the linear buffer is sent to a host using a direct memory access (DMA) operation responsive to a host request.