SSO Noise Estimation for Programmable Logic Devices
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Solution Overview
Problem
Conventional approaches fail to provide adequate design tools for predicting and addressing simultaneous switching output (SSO) noise in programmable logic devices (PLDs), leading to a tedious and time-consuming trial-and-error process during the design optimization, mapping, and routing stages.
Innovation Solution
A method is developed to collect and structure SSO noise data, including hardware and simulation data, to form data tables for calculations, and integrate an SSO noise estimator into the PLD design tool, allowing for automated worst-case SSO noise prediction and optimization of I/O signal assignments during the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SSO noise check tools are used after I/O signal assignments, then SSO noise can be detected, but the design process becomes tedious and time-consuming due to trial-and-error
Solution Approach 1:
The patent applies preliminary action by integrating SSO noise estimation into the design tool during the I/O signal assignment stage, allowing noise prediction to occur before final design decisions are made. This enables designers to anticipate and address SSO noise issues during the planning phase rather than detecting them afterward through time-consuming trial-and-error checks.
Solution Approach 2:
The patent implements feedback by providing real-time SSO noise estimation results within the design tool during the I/O assignment process. The system continuously monitors and feeds back noise predictions as signals are assigned, allowing designers to adjust assignments immediately based on noise feedback rather than waiting for separate analysis passes.
2Object-affected harmful factors
If more expensive packages (e.g., flip chip package) are used to reduce SSO noise, then SSO noise is reduced, but manufacturing cost increases
Solution Approach 1:
The patent applies parameter changes by systematically varying I/O signal assignment parameters (which signals are assigned to which pins) to minimize SSO noise. Instead of changing physical package parameters, the system optimizes electrical assignment parameters to achieve noise reduction at the same manufacturing cost.
Solution Approach 2:
The patent creates a computational model (copy) of the physical package's electrical characteristics to predict SSO noise behavior. This virtual model allows designers to evaluate different assignment scenarios and optimize noise performance without physically prototyping or changing expensive package types.
3Manufacturing precision
If SSO noise estimation is performed during design optimization, mapping, and route, then design quality improves, but computational complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the SSO noise estimation process into discrete computational steps that can be executed during different phases of design optimization. The noise calculation is broken down into manageable segments corresponding to individual I/O assignments, allowing incremental computation rather than requiring complete redesign analysis.
Solution Approach 2:
The patent uses simplified noise estimation models that provide sufficiently accurate predictions without requiring complex computational resources. These lightweight estimation algorithms act as disposable approximations that sacrifice some precision for speed, enabling repeated evaluations during design optimization without excessive computational burden.
Data Source
AI summary
Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output (SSO) noise data for an electronic device includes collecting hardware data on SSO noise conditions; generating additional data on SSO noise conditions based on the hardware data; and structuring the hardware data and the additional data to form data tables for SSO noise calculations.