SSPC Parallel Switch Fail-Open Detection Circuit
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Solution Overview
Problem
Conventional solid state power controller (SSPC) designs fail to detect open failures in switching devices, leading to potential overheating and reduced power quality due to increased current flow through remaining switches.
Innovation Solution
A fail open test circuit and power on built-in test (PBIT) system for SSPCs that individually test each switching device for open failures by controlling gate drivers and monitoring output voltage feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional monitoring methods are used to detect failed CLOSED conditions, then the detection of closed failures is achieved, but failed OPEN conditions cannot be detected
Solution Approach 1:
The patent segments the monitoring function by creating separate test circuits for each switching device. Instead of monitoring all switches collectively, the system individually tests each switch by isolating it with other switches in the OPEN state and applying a test voltage to detect OPEN failures specifically, while traditional methods continue to detect CLOSED failures.
Solution Approach 2:
The patent introduces a test voltage source and test circuit as an intermediary mechanism to detect OPEN failures. This intermediary test circuit applies a known voltage and measures the response through the switching device, enabling detection of OPEN conditions that traditional voltage monitoring cannot detect.
2Productivity
If multiple parallel solid state switches are used to achieve high current capabilities, then current sharing is improved, but undetected OPEN failures lead to overheating and reduced power quality
Solution Approach 1:
The patent implements preliminary detection by testing each switching device individually for OPEN failures before the system enters normal operation mode. The Power-On Built-In Test (POBIT) executes during startup, isolating and testing each switch with a dedicated test circuit, so that OPEN failures are detected before they can cause overheating or power quality issues during actual operation.
Solution Approach 2:
The patent establishes a feedback mechanism where the test circuit measures the response of each switching device and reports back to the controller. If an OPEN failure is detected, the system receives feedback about the specific failed device and can take corrective action, such as preventing normal operation or alerting the user, thereby maintaining system safety.
3Measurement precision
If individual testing of switching devices is implemented, then detection precision for OPEN failures is improved, but system complexity increases
Solution Approach 1:
The patent applies universality by designing a standardized test circuit architecture that can be replicated for each switching device using the same components and methodology. The test circuit uses universal elements (voltage source, measurement circuitry, isolation switches) that perform multiple functions: isolating the device under test, applying test voltage, measuring response, and reporting results. This modular approach maintains precision while controlling complexity through reuse.
Data Source
AI summary
A system includes a solid state power controller (SSPC) including a plurality of switching devices connected in parallel. A gate driver is operatively connected to control the plurality switching devices together so all of the switching devices in the plurality of switching devices either close to pass current through the SSPC, or open to prevent current passing through the SSPC in a normal operation mode. A fail open test circuit is operatively connected to individually control a respective gate of each of the switching devices in the plurality of switching devices for testing the plurality of switching devices individually for a fail OPEN condition.