Parallel SSPC Switch Testing for Fail-Open Detection
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Solution Overview
Problem
Conventional solid state power controller (SSPC) designs fail to detect open failures in parallel switches, leading to latent-for-life-failures, increased impedance, overheating, and potential safety issues due to unbalanced current distribution.
Innovation Solution
A system and method for fail open testing in SSPCs, where a gate driver and fail open test circuit individually control each switching device to test for open failures using a power on built-in test (PBIT) by setting a bias to pass a test current and evaluating output voltage feedback, with a voltage sensor providing indicative feedback for determining pass or fail conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional monitoring methods are used to detect failed CLOSED conditions, then the detection of closed failures is achieved, but failed OPEN conditions cannot be detected
Solution Approach 1:
The patent segments the monitoring function by creating separate test circuits for each parallel switching device. Each switching device is individually monitored by its own test circuit that can detect both failed CLOSED and failed OPEN conditions independently, rather than using a single collective monitoring method.
Solution Approach 2:
The patent introduces an intermediary test signal path that allows individual testing of each switching device. The test circuit uses intermediate test nodes and signals to isolate and evaluate each switching device's state without being affected by the states of other parallel devices.
2Productivity
If multiple parallel solid state switches are used to achieve high current capabilities, then current sharing is improved, but detection of open failures becomes impossible
Solution Approach 1:
The patent divides the monitoring function into separate segments, with each parallel switching device having its own dedicated test circuit. This segmentation allows individual detection of open failures in each device while maintaining the parallel configuration for high current capability.
Solution Approach 2:
The patent implements preliminary testing of each switching device before normal operation begins. The test circuits are activated during a test mode to evaluate the state of each switching device, allowing open failures to be detected before they affect system operation.
3Ease of operation
If a failed OPEN switch is not detected, then the system continues operation, but impedance increases and overheating occurs
Solution Approach 1:
The patent performs preliminary testing of each switching device before normal operation to detect open failures in advance. By testing each device individually during initialization, the system can identify and address open failures before they cause increased impedance and overheating during operation.
Solution Approach 2:
The patent implements feedback through test circuits that continuously monitor the state of each switching device. The test circuits provide feedback signals that indicate the operational status of each device, allowing the system to detect open failures and respond before thermal problems develop.
4Reliability
If individual testing of each switching device is implemented, then open failures can be detected, but system complexity increases
Solution Approach 1:
The patent uses universal test circuit designs that can be replicated for each switching device. The test circuits employ standard components and methodologies that are consistent across all parallel devices, reducing the complexity increment compared to custom individual testing solutions.
Solution Approach 2:
The patent segments the testing function into independent, modular test circuits for each switching device. Each test circuit is a self-contained unit that can be independently implemented and maintained, making the overall system manageable despite the increased number of components.
Data Source
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AI summary
A system includes a solid state power controller (SSPC) including a plurality of switching devices (102) connected in parallel. A gate driver is operatively connected to control the plurality switching devices (102) together so all of the switching devices (102) in the plurality of switching devices (102) either close to pass current through the SSPC, or open to prevent current passing through the SSPC in a normal operation mode. A fail open test circuit is operatively connected to individually control a respective gate of each of the switching devices (102) in the plurality of switching devices (102) for testing the plurality of switching devices (102) individually for a fail OPEN condition.