SSPC Thermal Memory Effect for Fuse Curve Coordination
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Solution Overview
Problem
Solid State Power Controllers (SSPCs) in commercial aircraft face safety concerns due to fail-short events and require additional protection mechanisms, which increase complexity and certification challenges, with existing methods either not addressing safety concerns or using unsuitable resistance and capacitance values for aerospace applications.
Innovation Solution
Implementing a thermal memory effect in SSPCs by dividing it into initial thermal memory and thermal memory due to overcurrent, using a capacitor that charges multiple times during overcurrent events and a discharging module with a resistor and second capacitor to simulate temperature evolution, allowing for practical semi-digital circuit implementations that coordinate with fuse characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thermal memory feature is used with an SSPC to mimic circuit breaker performance, then the SSPC can provide protection similar to traditional circuit breakers, but the circuit implementation requires resistance values not recommended for aerospace applications and capacitance values that cause high leakage and high variations in trip timing
Solution Approach 1:
The patent divides the thermal memory effect into two separate modules: an initial thermal memory module that handles pre-fault temperature conditions, and a thermal memory due to over current module that handles fault conditions. This segmentation allows each module to use optimized component values suitable for aerospace applications, avoiding the high leakage and timing variations caused by single large capacitance values.
Solution Approach 2:
The patent introduces a counter as an intermediary element between the capacitor charging/discharging mechanism and the trip decision logic. The counter accumulates charge events and provides a digital representation of thermal memory, which simplifies the control logic and allows for more precise trip timing control without requiring extremely large capacitance values.
2Reliability
If additional protection mechanism is associated with the SSPC to meet safety requirements, then safety and reliability requirements are met, but complexity is added to the use of SSPC technology
Solution Approach 1:
The patent combines the thermal memory protection mechanism directly into the SSPC controller itself, rather than using a separate external device. The initial thermal memory and over-current thermal memory modules are integrated within the SSPC, allowing the controller to monitor both normal and fault conditions and provide appropriate protection without requiring additional external protection devices.
Solution Approach 2:
The SSPC controller is designed to perform multiple functions: normal power control, initial thermal memory monitoring for pre-fault conditions, and over-current thermal memory monitoring for fault conditions. This multi-functionality eliminates the need for separate protection devices and reduces overall system complexity while maintaining comprehensive safety coverage.
3Measurement precision
If capacitor charges multiple times during over current condition to produce temperature count, then wire temperature increase is detected, but the electrical parameter associated with the count must decay with time to simulate wire cooling
Solution Approach 1:
The patent implements a feedback mechanism where the counter value, representing wire temperature, is continuously monitored and fed back to the control logic. The discharging module provides negative feedback by gradually reducing the counter value to simulate wire cooling, allowing the system to dynamically adjust trip decisions based on real-time thermal conditions without requiring complex external temperature sensors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thermal memory effect enables SSPCs to interrupt repetitive faulty currents sooner and achieve proper coordination with fuses, ensuring safety and meeting certification requirements by using practical resistor and capacitor values that avoid leakage and variations in trip timing, suitable for aerospace environments.
Implementation Method 1
a trip module including a first capacitor and a counter, wherein the first capacitor charges multiple times, when an over current event occurs, and the counter accumulates a count related to the charging of the first capacitor
Implementation Method 2
a discharging module connected to the trip module, the discharging module including a resistor and a second capacitor, wherein an electrical parameter associated with the count decays with time using the resistor and the second capacitor
Data Source
AI summary
Methods and apparatuses implement a thermal memory effect for a solid state power controller. A solid state power controller trip apparatus with thermal memory according to one embodiment comprises: a trip module including a first capacitor (156) and a counter (174), wherein the first capacitor (156) charges multiple times, when an over current event occurs, and the counter (174) accumulates a count related to the charging of the first capacitor (156) for the multiple times, to detect a trip condition; and a discharging module connected to the trip module, the discharging module including a resistor (166) and a second capacitor (158), wherein an electrical parameter associated with the count decays with time using the resistor (166) and the second capacitor (158).