Sub-Sampling PLL Feedback Edge Selection for Lower Phase Noise
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Solution Overview
Problem
Conventional phase locked loops (PLLs) face challenges in maintaining reference frequency signal stability and noise performance, particularly in sub-sampling PLLs, due to noise contributions from the phase detector and charge pump, which are exacerbated by frequency division in the feedback path.
Innovation Solution
A sub-sampling phase locked loop (SSPLL) design that omits the frequency divider, incorporates a multiplexer and selection control module to selectively supply signal edges or supply voltage, and includes an adaptive charge pump for improved noise performance and fast frequency locking, reducing the need for a secondary frequency locked loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency division is implemented in the feedback path of a conventional PLL, then the output frequency can be multiplied relative to the reference frequency, but the noise contributions from the phase detector and charge pump are exacerbated
Solution Approach 1:
The patent extracts and removes the frequency divider from the feedback path of the PLL. By eliminating the frequency division mechanism, the system achieves frequency multiplication through a different approach (direct VCO operation) while avoiding the noise exacerbation that occurs with conventional frequency division. This extraction of the problematic component resolves the contradiction between achieving high output frequency and minimizing phase noise.
2Loss of time
If a secondary frequency locked loop is added to achieve fast frequency locking, then the frequency lock speed improves, but the device complexity increases
Solution Approach 1:
The patent removes the secondary frequency locked loop from the system architecture. Instead of using a complex two-loop structure, the invention achieves fast frequency locking through a simplified single-loop design with direct VCO control and optimized feedback mechanisms. This extraction of the secondary loop eliminates the need for additional circuitry while maintaining fast lock performance, thereby resolving the contradiction between lock speed and system complexity.
3Measurement precision
If the VCO output is directly supplied to the phase detector, then the phase detection accuracy is maintained, but the in-band phase noise increases
Solution Approach 1:
The patent introduces an intermediary mechanism between the VCO output and the phase detector. Instead of direct connection, the system uses a buffered or conditioned feedback path that mediates the signal transmission. This intermediary structure allows accurate phase detection while filtering or isolating the in-band phase noise, thereby resolving the contradiction between measurement precision and noise reduction.
Data Source
AI summary
A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.