Super-Sampling Rate Block for RF Signal Processing
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Solution Overview
Problem
Conventional modeling environments for integrated circuits (ICs) are limited in handling vector or N-dimensional input/output data, which restricts their usability and capabilities in developing radio frequency (RF) applications, as they typically operate on scalar samples and cannot process gigahertz range RF signals efficiently due to the disparity between the maximum clock rate of programmable ICs and the sampling rate needed for RF signal processing.
Innovation Solution
The implementation of super-sampling rate (SSR) blocks in a model-based design tool's IP library, which can operate on N-dimensional data, allowing for the conversion of serial RF I/O data into multi-channel data, enabling programmable circuitry to process RF signals despite having a lower clock rate. These SSR blocks are configured with a parameter specifying the number of channels, allowing for parallel processing and automatic elaboration into scalar instances within the modeling environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional modeling environments operate on scalar samples, then the device complexity is reduced and ease of operation is improved, but the productivity is worsened due to inability to process gigahertz range RF signals efficiently
Solution Approach 1:
The patent introduces N-dimensional data structures into the modeling environment, allowing scalar samples to be extended into vectors with multiple channels. This dimensional transformation enables the processing of multiple RF signal channels simultaneously, achieving gigahertz range processing capability while maintaining the familiar scalar-based operational interface for users.
Solution Approach 2:
The patent creates a universal modeling environment that can handle both traditional scalar samples and N-dimensional vector data. The SSR blocks are designed to work with both data types, allowing the same modeling tool to process simple scalar signals and complex multi-channel RF vectors without requiring separate specialized environments, thus improving productivity without proportionally increasing complexity.
2Speed
If programmable ICs operate at lower clock rates, then the manufacturing precision and reliability are improved, but the speed is worsened due to inability to meet RF sampling rate requirements
Solution Approach 1:
The patent segments the high-speed RF sampling task into multiple parallel lower-speed processing channels. By dividing the N-dimensional input vector into multiple scalar channels that can be processed in parallel at lower clock rates, the system achieves the required effective sampling rate while allowing each individual processing element to operate reliably within its clock rate capabilities.
Solution Approach 2:
The patent transforms the time-domain speed limitation into a spatial parallelism solution. Instead of attempting to process all RF channels sequentially at high speed, the system uses the N-dimensional channel dimension to distribute the processing load across multiple parallel scalar instances, each operating at reliable lower clock rates while collectively achieving the required sampling rate.
3Adaptability or versatility
If conventional modeling environments handle only scalar data, then the device complexity is reduced, but the adaptability is worsened due to inability to process N-dimensional RF I/O data
Solution Approach 1:
The patent implements dynamic adaptability where the modeling environment can adjust its data handling mode based on the specific application requirements. The SSR blocks can dynamically process both scalar and N-dimensional vector data, allowing the system to adapt to different RF processing needs without requiring a completely different modeling environment structure, thus improving versatility with controlled complexity.
Data Source
AI summary
Circuit designs and/or circuitry for integrated circuits (ICs) can be generated for radio-frequency (RF) applications by determining, using computer hardware, a value of a parameter of a super-sampling rate (SSR) block within a model of a circuit, wherein the value indicates a number of a plurality of data channels of the SSR block, automatically creating, using the computer hardware, a primary input port and a primary output port for the SSR block based on functionality of the SSR block, wherein vector size of the primary input port and the primary output port is determined from the value of the parameter, automatically creating, using the computer hardware, a plurality of scalar instances of the SSR block based on the value of the parameter, wherein the plurality of scalar instances are arranged in parallel, and configuring, using the computer hardware, each scalar instance of the plurality of scalar instances based on a parameterization of the SSR block.