Full-Rate SST Transmitter Driver With Programmable Floating Taps
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Solution Overview
Problem
High-speed serializer/deserializer (SERDES) transmitter drivers face challenges in achieving high bandwidth, finite impulse response (FIR) range, low jitter, and low duty cycle distortion (DCD) at increasing data rates, particularly in high-performance CPU applications like Infini-band Enhanced Data Rate standards, due to design constraints on physical size and pin count.
Innovation Solution
A novel full-rate source-series-terminated (SST) transmitter driver architecture with programmable floating taps, multi-phase clocking, and phased clock error correction, along with optimized inductor structures that overlap output interface bumps, to achieve large FIR range and high channel equalization capability while maintaining low jitter and DCD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the I/O data rate is increased to meet growing data bandwidth demands, then data bandwidth is improved, but the difficulty of achieving high performance requirements (bandwidth, FIR range, jitter, DCD) increases
Solution Approach 1:
The transmitter driver is divided into multiple independent slices (e.g., 4 slices), each handling a portion of the data lanes. Each slice contains its own multiplexer, driver, and output circuitry, allowing parallel processing and reducing the complexity burden on any single component while achieving high aggregate data bandwidth
Solution Approach 2:
The transmitter driver uses programmable floating taps with adjustable weights that can be dynamically configured to optimize performance for different channel conditions and data rates. The multi-phase clocking system also provides dynamic phase adjustment capability to maintain low jitter across varying operating conditions
2Speed
If the SERDES operating speed is increased to achieve higher I/O data rates, then data rate is improved, but maintaining low jitter and low duty cycle distortion becomes more difficult
Solution Approach 1:
The system employs multi-phase clocking with periodic phase sampling and error correction. The phased clock error correction mechanism periodically measures and corrects phase deviations, maintaining low jitter performance even at high data rates by resetting accumulated phase errors before they degrade signal quality
Solution Approach 2:
The transmitter driver incorporates feedback mechanisms where the output signal characteristics are monitored and used to adjust the floating tap weights and clock phase alignment. This closed-loop control maintains low duty cycle distortion and jitter by continuously compensating for deviations caused by high-speed operation
3Area of stationary object
If the CPU physical size and pin count are constrained, then integration density is improved, but achieving high data bandwidth becomes more difficult
Solution Approach 1:
The patent transitions from parallel data lanes to time-division multiplexed serial transmission. By encoding multiple data streams in the time domain using multi-phase clocking and sequential transmission through fewer pins, the system achieves high effective bandwidth while reducing the physical pin count requirement
Solution Approach 2:
Each transmitter driver slice is designed as a universal building block that can handle multiple data lanes and be configured for different data rates. The programmable floating taps and multi-phase clocking provide multi-functionality, allowing the same hardware structure to achieve high bandwidth across various operating conditions without requiring additional physical resources
Data Source
AI summary
Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.