Impedance Calibration for Source Series Terminated Transmitters
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Solution Overview
Problem
Conventional high-speed serializer/deserializer standards require precise differential output impedance, which is challenging to maintain with smaller field effect transistors due to their larger impedance variations, leading to inaccuracies in transmitter performance, especially at high-speed transmission frequencies.
Innovation Solution
A method and system for calibrating the output impedance of a device-under-test using a feedback control signal and a finite state machine to adjust the impedance of parallel transistors in series with a resistor, ensuring the impedance falls within a predetermined range by comparing it to a reference resistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If smaller FETs are used to support higher transmission speeds, then transmission rate is improved, but FET impedance increases causing output impedance to fall out of the required range
Solution Approach 1:
The FET is divided into multiple parallel-connected FETs (first FET and second FET) that can be independently controlled. By selectively turning on or off individual FETs, the total impedance can be adjusted in discrete steps to achieve the desired output impedance range while maintaining high-speed transmission capability.
Solution Approach 2:
The impedance of the FET network is made dynamically adjustable through control signals that turn individual FETs on or off based on detected impedance conditions. This dynamic adjustment allows the system to adapt to process variations and maintain accurate output impedance while using smaller, high-speed FETs.
2Manufacturing precision
If FET impedance is reduced to meet output impedance requirements, then output impedance accuracy is improved, but transmission speed capability deteriorates
Solution Approach 1:
Instead of using a single large FET with low impedance, the system uses multiple smaller FETs in parallel. Each FET can be independently controlled, allowing the system to achieve the required low impedance when needed while maintaining the ability to operate at high speeds that would be impossible with a single large FET.
Solution Approach 2:
Multiple FETs are combined in parallel to achieve the desired impedance characteristics. The parallel combination allows the system to leverage the high-speed capability of smaller FETs while achieving the low equivalent impedance needed for accurate output impedance through proper switching combinations.
3Adaptability or versatility
If process and voltage variations are accommodated to ensure reliability, then adaptability is improved, but output impedance control worsens
Solution Approach 1:
The system incorporates feedback mechanisms that detect the actual impedance conditions and adjust the control signals to individual FETs accordingly. This feedback loop compensates for process and voltage variations by dynamically reconfiguring the FET network to maintain accurate output impedance despite environmental changes.
Solution Approach 2:
The system changes the operational parameters (on/off states) of individual FETs based on detected conditions. By monitoring impedance and adjusting which FETs are active, the system can compensate for process variations and voltage changes while maintaining the required output impedance accuracy.
Data Source
AI summary
Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.