Statistical Static Timing Analysis Memory Conservation

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Solution Overview

Problem

Conventional statistical static timing analysis (SSTA) requires significant memory resources due to the need to store complete statistical descriptions of timing quantities, which can be prohibitive for large integrated circuit designs, especially as the number of sources of variation increases.

Innovation Solution

Implement a method that persistently stores timing data at constraint points in the timing graph, allowing for the calculation of intermediate data on demand, thereby reducing memory requirements and recalculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If complete statistical descriptions of timing quantities are stored at all nodes in SSTA, then timing analysis accuracy is improved, but memory resource consumption increases significantly

Engineering Contradiction:
Improvetiming analysis accuracyVSAvoidmemory resource consumption
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the timing graph nodes into two categories: constraint points and intermediate nodes. Complete statistical descriptions are stored only at constraint points, while intermediate nodes use deterministic values. This segmentation allows the system to maintain timing analysis accuracy at critical points while significantly reducing overall memory consumption by avoiding redundant storage at non-critical intermediate nodes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by storing complete statistical descriptions (higher quality data) selectively at constraint points where timing validation is critical, while using simpler deterministic values at intermediate nodes. This localized approach ensures that accuracy is maintained where it matters most for timing verification while reducing memory usage in less critical areas of the timing graph.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple STA timing runs are executed to cover the entire process space, then comprehensive timing coverage is improved, but computational cost and time increase prohibitively

Engineering Contradiction:
Improvetiming coverageVSAvoidcomputational time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by conducting a single SSTA timing run that propagates statistical distributions through the entire timing graph. This preliminary statistical analysis captures the behavior across the entire process space in one execution, eliminating the need for multiple separate STA runs at different corners and significantly reducing computational time while maintaining comprehensive timing coverage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter representation from deterministic single values to statistical distributions. By propagating mean and variance (or other statistical moments) through the timing graph in a single SSTA run, the method captures the effects of process variations across the entire process space, providing comprehensive timing coverage that would otherwise require multiple STA runs at different process corners.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7849429B2Methods for conserving memory in statistical static timing analysis
Publication Date: 2010.12.07 SIEMENS INDUSTRY SOFTWARE INC
  • US7849429B2 patent drawing
  • US7849429B2 patent drawing
  • US7849429B2 patent drawing

AI summary

A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis.