SSTA Tool for Non-Gaussian Variation Analysis in Multi-Phase Circuits
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Solution Overview
Problem
Current Statistical Static Timing Analysis (SSTA) tools face challenges in accurately handling non-Gaussian variation effects for both gate and interconnect delays in multi-phase sequential circuits, particularly in calculating critical paths and characterizing timing libraries with complex timing constraints and cross-talk issues.
Innovation Solution
The development of a SSTA tool that employs path analysis using forward breadth-first search and backward depth-first traversal to generate critical paths considering non-Gaussian variations up to quadratic order, pre-characterizing timing libraries, and calculating admittance matrices and voltage transfers with second-order variation effects to accurately model gate and interconnect delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SSTA tools use Gaussian distribution for delay analysis, then the analysis is computationally simpler, but the accuracy is insufficient for capturing non-Gaussian variation effects in multi-phase sequential circuits
Solution Approach 1:
The patent transforms the delay distribution representation from simple Gaussian to a sum of Gaussian variables expanded to second-order terms. This parameter change allows capturing non-Gaussian characteristics while maintaining computational tractability through systematic expansion methods.
Solution Approach 2:
The patent introduces intermediate representations including characteristic functions and cumulant expansions as mediators between the raw non-Gaussian delay data and the final timing analysis results. These intermediaries facilitate the mathematical transformation and computation of second-order effects.
2Reliability
If the SSTA tool includes interconnect effects with process variation, then the timing analysis becomes more comprehensive, but the computational complexity increases significantly
Solution Approach 1:
The patent segments the interconnect delay analysis into manageable components by applying second-order expansion to specific delay elements and using effective capacitance models for interconnect segments. This segmentation allows handling complex interconnect effects without overwhelming computational burden.
Solution Approach 2:
The patent applies second-order analysis selectively to critical path elements and interconnect segments where non-Gaussian effects are most significant, rather than uniformly to the entire circuit. This partial application of the complex method optimizes the balance between accuracy and computational resources.
3Measurement precision
If the tool pre-characterizes timing libraries to second order, then the accuracy of gate delay modeling improves, but the library characterization process becomes more complex
Solution Approach 1:
The patent performs preliminary second-order characterization of timing libraries during the library preparation phase, before actual circuit timing analysis. This preliminary action pre-computes the necessary second-order parameters and stores them in enhanced timing library formats, making the subsequent circuit analysis more efficient.
Solution Approach 2:
The patent creates enhanced copies of standard timing library cells that include second-order variation parameters. These copied library representations maintain compatibility with existing design flows while incorporating the additional accuracy information needed for precise timing analysis.
Data Source
AI summary
In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.