Self-Aligned STI Using Bitline Oxide for Leakage Prevention
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Solution Overview
Problem
The challenge in semiconductor memory arrays is the misalignment of bitline contacts during fabrication, which can lead to leakage and requires additional masking steps to ensure proper alignment and functionality.
Innovation Solution
The formation of self-aligned silicon trench isolation (STI) between adjacent bitlines, which is independent of CMOS periphery requirements and allows for shallower trench depths, preventing misaligned contacts from contacting underlying silicon and eliminating the need for additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bitline contact formation is used, then contacts can be formed, but misalignment occurs leading to leakage and requiring additional masking steps
Solution Approach 1:
The bitline oxide serves as a self-aligned mask for trench formation. The oxide is formed over the bitline, then trenches are etched using the oxide as the masking layer, ensuring automatic alignment between the trench and bitline without requiring separate alignment steps or additional masks.
Solution Approach 2:
The bitline oxide is formed in advance before trench formation. This preliminary oxide layer establishes the alignment reference for subsequent trench etching, ensuring that trenches are automatically positioned relative to bitlines before the actual contact formation occurs.
2Ease of manufacture
If shallower trench depths are used, then fabrication is simplified, but alignment precision may be compromised
Solution Approach 1:
The bitline oxide automatically serves as the alignment reference for trench formation. Since the oxide is formed directly over the bitline and then used as the mask for trench etching, the trench depth can be reduced without compromising alignment precision—the oxide ensures precise positioning regardless of trench depth.
3Manufacturing precision
If additional masking steps are added, then alignment precision improves, but fabrication complexity and time increase
Solution Approach 1:
The bitline oxide performs dual functions: it protects the bitline during processing and serves as the mask for trench formation. This eliminates the need for separate alignment masks, reducing the number of fabrication steps while maintaining precise alignment between trenches and bitlines.
Solution Approach 2:
The bitline oxide serves multiple functions simultaneously: it acts as a protective layer over the bitline, a mask for trench etching, and an alignment reference. This multi-functionality consolidates multiple process steps into one, improving fabrication efficiency without sacrificing precision.
Data Source
AI summary
Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices.