ST-MRAM ECC Write Scheme Using Majority Bit Inversion
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Solution Overview
Problem
Spin-torque magnetoresistive random access memory (ST-MRAM) faces challenges in scalability due to increasing variability in magnetic tunnel junction (MTJ) resistance and high switching currents, which limit its ability to maintain high density and fast write speeds, and the integration of error correction codes (ECC) further delays memory access.
Innovation Solution
A method and apparatus for reading and writing ST-MRAM that employs ECC, calculates error correction bits using either an even or odd number of data bits, inverts data bits based on majority detection, and stores inversion status bits to minimize write current pulses and reduce power consumption, thereby managing memory access delays in high-bandwidth systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes (ECC) are integrated into ST-MRAM, then data integrity is improved, but memory access time increases
Solution Approach 1:
The patent performs ECC calculations and majority detection in advance during the write operation preparation phase, before the actual memory write occurs. This preliminary processing allows error correction to be ready beforehand, reducing the impact on memory access time while maintaining data integrity.
Solution Approach 2:
The patent integrates ECC operations into the existing memory access pipeline, allowing error correction calculations to proceed continuously alongside normal memory operations rather than as separate interrupting steps, thereby minimizing additional access time delays.
2Speed
If write current pulse duration is reduced, then write speed is improved, but switching current requirements increase
Solution Approach 1:
The patent employs majority detection and data inversion techniques that change the operational parameters of write operations. By detecting the majority state and inverting data when beneficial, the system optimizes current pulse characteristics, reducing the duration and magnitude of switching currents while maintaining effective writing speed.
Solution Approach 2:
The majority detection mechanism allows the memory system to automatically determine the optimal write strategy based on the current state of data bits, self-adjusting the current pulse parameters to minimize power consumption while achieving the required write speed.
3Quantity of substance
If MTJ dimensions are decreased, then storage density is improved, but resistance variability increases
Solution Approach 1:
The patent implements majority detection that monitors the resistance states of multiple MTJ cells and uses this feedback information to determine the appropriate write operation. This feedback mechanism compensates for resistance variability by detecting the collective state rather than relying on individual cell resistance precision, enabling higher density with smaller MTJ dimensions.
Solution Approach 2:
By changing from individual cell read/write operations to majority-based operations that consider multiple cells, the patent transforms the operational parameters to be more tolerant of resistance variability, allowing smaller MTJ dimensions and higher storage density without being constrained by manufacturing precision limitations.
4Ease of operation
If select device current capacity is increased, then write capability is improved, but device complexity increases
Solution Approach 1:
The patent uses majority detection to determine whether a write operation is actually needed by comparing the new data with the existing majority state. This partial action approach avoids unnecessary write operations, reducing the current capacity requirements of select devices while maintaining full write capability when needed, thereby reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces memory write operation time, minimizes power consumption, and enhances data integrity by efficiently managing write current pulses and error correction, thereby improving the scalability and performance of ST-MRAM.
Implementation Method 1
The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer
Implementation Method 2
exhibits an electrical resistance that depends on the magnetic state of the device
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.