Static Timing Analysis CPPR for Interdependency Pessimism Removal
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Solution Overview
Problem
Existing static timing analysis (STA) tools introduce excessive pessimism during common path pessimism removal (CPPR), which can increase design complexity and resource requirements, particularly in complex integrated circuits (ICs), by failing to account for interdependencies between circuit elements.
Innovation Solution
An iterative and levelized approach to common path pessimism removal (CPPR) analysis is applied, processing candidate circuit elements in parallel and sorting inputs by arrival time (AT) levels, updating timing performance adjustments, and iteratively refining CPPR adjustments until no further changes are needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If common path pessimism removal (CPPR) analysis is performed during static timing analysis, then timing accuracy is improved, but additional pessimism is introduced due to interdependencies between circuit elements
Solution Approach 1:
The patent segments the circuit elements into different dependency groups based on their interdependency relationships. By dividing the circuit into independent segments, the analysis can process each segment separately, avoiding the propagation of pessimism across dependent elements while maintaining timing accuracy within each segment.
Solution Approach 2:
The patent applies local quality by treating different circuit elements with different analysis approaches based on their specific interdependency characteristics. Elements with strong interdependencies are analyzed with localized timing adjustments, while independent elements receive standard CPPR analysis, thereby reducing unnecessary pessimism in specific regions without compromising overall timing accuracy.
2Measurement precision
If iterative CPPR analysis is performed on all candidate circuit elements, then timing performance is improved, but processing time and computational resources increase
Solution Approach 1:
The patent segments the candidate circuit elements into groups based on their interdependency relationships and processes each segment in parallel. This segmentation allows the iterative CPPR analysis to be distributed across multiple processing threads, reducing overall processing time while maintaining the accuracy benefits of iterative analysis.
Solution Approach 2:
The patent performs preliminary classification of circuit elements into dependency groups before initiating the iterative CPPR analysis. This preliminary action organizes the data structure to facilitate efficient parallel processing, avoiding redundant computations and reducing the total processing time required for iterative analysis.
3Productivity
If circuit elements with interdependencies are analyzed independently, then processing efficiency is improved, but timing accuracy deteriorates due to unaccounted interdependencies
Solution Approach 1:
The patent segments circuit elements into independent analysis groups based on their interdependency relationships. Elements within each segment are analyzed together to preserve timing accuracy, while segments themselves are processed independently to maintain processing efficiency. This segmentation strategy ensures that interdependencies are respected within groups without sacrificing overall productivity.
Solution Approach 2:
The patent implements a dynamic analysis approach where the level of detail in timing analysis is adjusted based on the interdependency characteristics of each circuit element group. Highly interdependent elements receive more detailed analysis to ensure timing accuracy, while less interdependent elements are processed with standard efficiency-oriented methods, creating a balanced approach between accuracy and productivity.
Data Source
AI summary
Embodiments of the invention are directed to a computer-implemented method of analyzing timing constraints of a component-under-design (CUD). The computer-implemented method includes performing an initial iteration of a common path pessimism removal (CPPR) analysis on circuit elements of the CUD. The circuit elements includes inputs and outputs, and the circuit elements further include a transparent circuit element. The computer-implemented method further includes storing an initial list of the inputs and the outputs for which timing was adjusted during the initial iteration; and applying a second iteration of the CPPR analysis to the initial list of the inputs and the outputs.