Static Timing Analysis Device History Bound Propagation
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Solution Overview
Problem
Static timing analysis (STA) is overly pessimistic due to unaccounted delay variations caused by device history, leading to artificial constraints on integrated circuit performance, as existing methods either assume extreme ranges of device history or require costly enumeration of sub-paths.
Innovation Solution
A method and system for adjusting delay variations by propagating bounds on device history through the timing graph, allowing for the reduction of pessimism by scaling or modifying delay components based on actual signal history, thereby refining delay estimates during STA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extreme ranges of device history are assumed to account for all possible variations, then timing analysis reliability is improved, but pessimism in timing estimates increases
Solution Approach 1:
The patent performs preliminary propagation of history bounds through the timing graph before conducting timing analysis. By pre-computing which signals have bounded histories and propagating these bounds through the circuit, the method prepares information that allows selective reduction of delay variation during the actual timing analysis, thus reducing pessimism while maintaining reliability.
Solution Approach 2:
The patent applies different delay variation treatments to different signals based on their individual history bound properties. Instead of uniformly applying extreme delay ranges to all signals, the method locally adjusts delay variation for signals whose histories are known to be bounded, while maintaining conservative estimates for signals with unknown histories. This localized approach reduces overall pessimism without compromising timing analysis reliability.
2Measurement precision
If actual signal history is used to adjust delay variation, then timing estimate accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent performs preliminary propagation of history bounds through the timing graph before conducting timing analysis. By pre-computing which signals have bounded histories and propagating these bounds through the circuit, the method prepares information that allows selective reduction of delay variation during the actual timing analysis, thus reducing pessimism while maintaining reliability.
Solution Approach 2:
The patent applies different delay variation treatments to different signals based on their individual history bound properties. Instead of uniformly applying extreme delay ranges to all signals, the method locally adjusts delay variation for signals whose histories are known to be bounded, while maintaining conservative estimates for signals with unknown histories. This localized approach reduces overall pessimism without compromising timing analysis reliability.
3Measurement precision
If path enumeration is performed to account for device history effects, then timing analysis accuracy is improved, but computational cost increases significantly
Solution Approach 1:
The patent extracts and propagates history bound information through the timing graph, separating the history analysis from the full path enumeration process. By extracting relevant history bounds and using them to directly adjust delay variation in the block-based STA approach, the method achieves accurate timing estimates without the exponential computational cost of enumerating all possible paths.
Solution Approach 2:
The patent creates a simplified representation of device history in the form of propagated history bounds, which serves as a proxy for the full device history information. This copied representation allows the timing analysis to account for history effects without needing to examine or enumerate actual device history sequences, dramatically reducing computational requirements.
Data Source
AI summary
A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.