Static Timing Analysis Partitioning for Memory Efficiency
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Solution Overview
Problem
The increasing complexity and size of integrated circuits make static timing analysis (STA) both time-consuming and resource-intensive, often becoming a bottleneck in the design flow, especially for large AI chips, due to high memory requirements and the risk of missing critical paths when performing STA on a single machine.
Innovation Solution
The method involves partitioning a circuit design into multiple overlapping partitions based on its structure, allowing for parallel processing across multiple machines, reducing memory requirements and runtime by performing STA on each partition independently while maintaining the integrity of timing paths and using a topological cone for analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STA is performed on a single machine with huge physical memory, then complete timing analysis can be achieved, but the process becomes extremely time-consuming and resource-intensive
Solution Approach 1:
The circuit design is divided into multiple partitions based on topological cones, where each partition represents a subset of the circuit with its associated timing constraints. This segmentation allows the STA problem to be distributed across multiple machines, reducing the time required for analysis while maintaining comprehensive coverage of all timing paths through proper partition overlap.
2Productivity
If the circuit design is partitioned into multiple partitions, then parallel processing can be performed to reduce runtime, but memory requirements and coordination complexity increase
Solution Approach 1:
The patent introduces a hierarchical dimension to the partitioning strategy by organizing partitions into levels based on their topological relationships. This dimensional organization allows for systematic management of partition dependencies and intersections, reducing the coordination complexity that would otherwise arise from arbitrary partitioning while enabling efficient parallel processing.
3Quantity of substance
If iterative flows are used to perform STA on large designs, then memory requirements are reduced, but the risk of missing critical paths increases
Solution Approach 1:
The patent performs preliminary identification of all topological cones and their relationships before executing the STA algorithm. By pre-establishing the complete set of partitions and their intersections, the system ensures that all potential critical paths are covered in the analysis without requiring iterative approaches, thus maintaining detection accuracy while reducing memory requirements through distributed processing.
Data Source
AI summary
A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.