Static Timing Analysis Wire-Thru Resistance Transformation
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Solution Overview
Problem
Current static timing analysis (STA) tools fail to accurately characterize leaf cell delay due to neglecting wire-thru resistances inside leaf cells, leading to potential timing violations and inaccuracies in timing analysis of memory circuits.
Innovation Solution
Transforming local wire through resistances into global distributed resistances by determining port-to-port resistances and promoting them to a hierarchical level above the leaf cells, allowing STA tools to recognize and account for internal parasitic resistances, thereby improving the accuracy of transient analysis and timing characterization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional transient analysis is used to accurately characterize timing, then measurement precision is improved, but productivity deteriorates due to massive computational resource consumption
Solution Approach 1:
The patent segments the complex transient analysis problem into two parts: (1) pre-compute equivalent resistances for leaf cells using transient analysis, and (2) use these pre-computed values in static timing analysis. This segmentation allows the computationally intensive transient analysis to be performed only once per leaf cell type, rather than for every instance, thereby improving productivity while maintaining measurement precision.
Solution Approach 2:
The patent performs preliminary computation of equivalent resistances for leaf cells before the main timing analysis. By pre-computing these resistance values and storing them in a library, the system eliminates the need to perform full transient analysis during the timing verification phase, thus resolving the contradiction between accuracy and computational efficiency.
2Productivity
If static timing analysis is used to improve productivity, then computational efficiency is improved, but measurement precision deteriorates due to inability to account for wire-thru resistances
Solution Approach 1:
The patent introduces an intermediary element - the equivalent resistance value - that bridges static timing analysis and transient analysis. This equivalent resistance, computed once per leaf cell type through transient analysis, serves as a mediator that allows STA to account for wire-thru resistance effects without performing full transient analysis, thus improving measurement precision while maintaining productivity.
Solution Approach 2:
The patent transforms the physical wire-thru resistance inside leaf cells into an equivalent resistance parameter that can be used in static timing analysis. By changing the representation of resistance from a distributed physical parameter to a lumped equivalent parameter, the system enables accurate timing analysis using efficient STA methods.
3Measurement precision
If wire-thru resistances are included in timing analysis, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the wire-thru resistance effect from the complex internal structure of leaf cells and represents it as a separate equivalent resistance parameter. By taking out this specific resistance component and treating it independently in the timing analysis model, the system improves measurement precision while avoiding the complexity of modeling the entire internal cell structure.
Data Source
AI summary
A method for transient analysis of a memory module circuit, the method including: determining port to port resistances between terminals of internal circuits of a plurality of leaf cells of a netlist representing the memory module circuit; generating a plurality of equivalent networks corresponding to the internal circuits of the leaf cells, the equivalent networks being connected to each other; promoting the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the netlist representing the memory module circuit; shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks; and performing the transient analysis of the leaf cells of the netlist representing the memory module circuit.