Stable Memory Cell Identification via Power Cycling

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Solution Overview

Problem

Current methods for selecting stable memory cells for hardware security applications, such as Temporal Majority Voting (TMV), require numerous tests and introduce hardware overhead, and are not effective in ensuring stability under extreme environmental conditions.

Innovation Solution

A method involving brief power-down and power-up cycles to identify stable memory cells based on data remanence, reducing test time and improving stability by selecting cells that maintain their state across varying conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Temporal Majority Voting (TMV) is used to select stable memory cells, then stability under environmental conditions is improved, but test time and hardware overhead increase

Engineering Contradiction:
Improvestability of memory cellsVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts only the essential characteristic needed for stability testing by applying brief power-down cycles that exploit data remanence. Instead of performing numerous repetitive tests as in TMV, the invention isolates the key property (data remanence during power-down) to identify stable cells, thereby dramatically reducing test time while maintaining reliability assessment.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention changes the testing parameter from repetitive operational tests to brief power-down cycles with specific duration. By adjusting the power-down time parameter, the method efficiently distinguishes stable cells (which retain data) from unstable cells (which lose data), achieving reliable identification without the time-consuming repetitive testing of traditional TMV approaches.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If numerous tests are performed to ensure stability, then measurement precision is improved, but productivity decreases

Engineering Contradiction:
Improveaccuracy of stability identificationVSAvoidtest throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent performs preliminary action by applying brief power-down cycles that immediately reveal stability characteristics through data remanence. This preliminary test approach provides sufficient measurement precision to identify stable cells without requiring numerous subsequent repetitive tests, thereby maintaining accuracy while significantly improving test throughput and productivity.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If traditional stability testing methods are used, then comprehensive testing is achieved, but device complexity increases

Engineering Contradiction:
Improvestability verificationVSAvoidtest hardware overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention enables self-service testing by utilizing the memory cells' own data remanence property during brief power-down cycles. The cells inherently reveal their stability status without requiring complex external testing hardware or control mechanisms, thereby achieving reliable stability verification while minimizing device complexity and hardware overhead.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces test time and improves the accuracy of selecting stable cells, ensuring they remain stable under extreme conditions, including temperature and voltage variations, and device aging.

Implementation Method 1

A method involves brief power-down and power-up cycles to identify stable memory cells based on data remanence

Methodology Applied
Scientific EffectData remanence:

Data Source

PatentUS11769548B2Stable memory cell identification for hardware security
Publication Date: 2023.09.26 REGENTS OF THE UNIVERSITY OF MINNESOTA
  • US11769548B2 patent drawing
  • US11769548B2 patent drawing
  • US11769548B2 patent drawing

AI summary

A method includes setting an output of each memory cell in an array of memory cells to a same first value, decreasing power to the array of memory cells and then increasing power to the array of memory cells. Memory cells in the array of memory cells with outputs that switched to a second value different from the first value are then identified in response to decreasing and then increasing the power. A set of memory cells is then selected from the identified memory cells to use in hardware security.