Stack Cache Manager Coherence for Multicore Processors
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Solution Overview
Problem
In multicore processor systems, managing stack data coherence across execution cores is inefficient due to the need for reverse address translations and frequent cache snooping, which consumes energy and generates unnecessary coherence traffic.
Innovation Solution
A processor system with a stack cache manager that maintains status entries for stack data accessed by execution cores, allowing virtual address-based retrieval and reducing the need for reverse address translations by tracking ownership and using a centralized page table to maintain coherence across stack caches and TLBs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache management with reverse address translations and cache snooping is used, then stack data coherence can be maintained, but energy consumption increases and coherence traffic becomes excessive
Solution Approach 1:
The patent extracts the coherence management function from the traditional cache snooping mechanism and relocates it to the stack cache manager. By maintaining a separate status table that tracks stack data ownership and coherence state, the system eliminates the need for continuous cache snooping operations, thereby reducing energy consumption while preserving coherence guarantees.
Solution Approach 2:
The stack cache manager acts as an intermediary between execution cores and the stack data. It maintains a centralized status table that mediates coherence decisions, eliminating the need for direct cache snooping operations. This intermediary structure resolves coherence conflicts without requiring energy-intensive snoop messages across the inter-core communication infrastructure.
2Reliability
If reverse address translations are performed frequently, then stack data coherence can be verified, but coherence traffic increases unnecessarily
Solution Approach 1:
The stack cache manager performs preliminary tracking of stack data ownership and coherence state in its status table before coherence conflicts arise. By maintaining this advance knowledge of data location and ownership, the system can make coherent access decisions without needing to perform reverse address translations or generate coherence traffic when conflicts occur.
Solution Approach 2:
Instead of relying on actual cache snooping operations to verify coherence, the system creates a virtual copy of coherence state information in the stack cache manager's status table. This copied information allows the system to track coherence state without generating physical coherence traffic, as the status table maintains the coherence state as metadata rather than requiring active verification messages.
3Productivity
If stack data is managed with centralized tracking, then coherence efficiency improves, but device complexity increases
Solution Approach 1:
The stack cache manager is designed as a multi-functional component that handles both stack data coherence management and virtual address translation coordination. By combining these functions in a single centralized structure, the patent avoids the need for separate coherence management hardware, thereby limiting the increase in device complexity while achieving high coherence efficiency.
Data Source
AI summary
A processor system presented here has a plurality of execution cores and a plurality of stack caches, wherein each of the stack caches is associated with a different one of the execution cores. A method of managing stack data for the processor system is presented here. The method maintains a stack cache manager for the plurality of execution cores. The stack cache manager includes entries for stack data accessed by the plurality of execution cores. The method processes, for a requesting execution core of the plurality of execution cores, a virtual address for requested stack data. The method continues by accessing the stack cache manager to search for an entry of the stack cache manager that includes the virtual address for requested stack data, and using information in the entry to retrieve the requested stack data.