Stack Die Self-Test Access for Early Defect Detection
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining circuit robustness and failure detectability while increasing circuit density and reducing device footprint, leading to manufacturing defects that are difficult to identify after integration into a stack.
Innovation Solution
Incorporating a stack testing mechanism within each die in a semiconductor device that enables communicative access and adaptability of die-level self-test circuits, allowing for testing of individual dies within a stack before integration, using TSVs and die identifier circuits to facilitate early defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit density is increased and device footprint is reduced, then productivity and device performance are improved, but manufacturing precision and failure detectability deteriorate
Solution Approach 1:
The patent divides the monolithic semiconductor device into multiple stacked dies, each containing a portion of the circuit functionality. This segmentation allows for increased overall device performance while maintaining the ability to test and detect failures at the individual die level, thus resolving the contradiction between improved productivity and deteriorating manufacturing precision.
Solution Approach 2:
The patent implements preliminary testing mechanisms at the wafer level before the dies are fully integrated into the final stacked device. This preliminary action enables early detection of manufacturing defects, allowing for corrective measures to be taken before the device is completed, thereby maintaining manufacturing precision while achieving high device performance.
2Productivity
If circuit density is increased within a given physical area, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture. By adding the vertical dimension, the device achieves higher circuit density within the same footprint while organizing complexity into manageable stacked layers, each with its own testing capabilities.
Solution Approach 2:
The patent implements a nested testing structure where wafer-level test circuits are embedded within each die, and these dies are then stacked to form the final device. This nesting allows testing functionality to be integrated at multiple levels, managing the complexity of high-density 3D stacking through hierarchical organization.
3Manufacturing precision
If wafer-level self-test circuits are used, then manufacturing precision is improved, but device complexity increases due to additional test circuitry
Solution Approach 1:
The patent designs the wafer-level test circuits to serve multiple functions: they enable testing at the wafer level during manufacturing, continue to function after die stacking, and can be accessed through the final device interface. This multi-functionality reduces the need for separate dedicated test circuitry, thereby limiting the increase in device complexity while maintaining improved defect detection capability.
Data Source
AI summary
An apparatus including a stack testing mechanism and associated systems and methods are disclosed herein. The stack testing mechanism may be configured to test individual dies after they are stacked together. The stack testing mechanism may include circuits to separately identify and access individual dies, and based on the individual access, utilize self-test circuits within each die to test functionality of the corresponding die.