Stack Gate Flash Memory Scaling Below 0.25 Micron
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Solution Overview
Problem
Conventional split gate structure in Flash memory devices faces challenges in scaling below 0.25 micron due to size limitations and complexity, making it difficult to shrink and maintain efficiency.
Innovation Solution
A method and structure for manufacturing Flash memory devices using a stack gate structure with a first polysilicon layer, a dielectric layer, and a second polysilicon layer, where the select device is formed by patterning the stack layer to create a denser and more efficient memory cell design, allowing for easier scaling and higher device yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a split gate structure is used in Flash memory devices, then the device can be manufactured with conventional processes, but the device size cannot be scaled below 0.25 micron due to size limitations and complexity
Solution Approach 1:
The patent transitions from a planar split gate structure to a three-dimensional stacked gate structure. The control gate is positioned vertically above the floating gate, utilizing the vertical dimension to achieve higher integration density. This stacked configuration allows the memory cell to scale in the lateral plane while maintaining the necessary gate structures, thereby enabling scaling below 0.25 micron while preserving manufacturability through conventional adapted processes.
Solution Approach 2:
The patent implements a nested gate structure where the control gate encompasses the floating gate in a vertical stack configuration. The control gate is formed over the floating gate, with the tunnel dielectric layer positioned between them, creating a nested arrangement that reduces lateral footprint while maintaining functional separation. This nesting allows both gate structures to coexist in a compact vertical arrangement, enabling further miniaturization.
2Ease of manufacture
If a split gate structure is used in Flash memory devices, then the device can be manufactured with conventional processes, but the structural complexity increases making it difficult to shrink
Solution Approach 1:
By moving to a vertical stacked architecture, the patent reduces lateral complexity while introducing vertical layering. The control gate and floating gate are stacked vertically rather than arranged laterally, which simplifies the planar layout and routing. This dimensional transition allows conventional manufacturing processes to be adapted more easily to the new structure, reducing the overall structural complexity despite the vertical stacking.
Solution Approach 2:
The patent segments the gate structure into distinct vertical layers: the floating gate layer, tunnel dielectric layer, and control gate layer. Each layer is formed and patterned separately through sequential deposition and etching steps. This segmentation allows each component to be optimized independently while maintaining overall structural simplicity, making the device easier to manufacture and shrink compared to the interconnected split gate structure.
3Quantity of substance
If a stacked gate structure is used, then the device density increases and scaling becomes easier, but new manufacturing processes are required
Solution Approach 1:
The patent employs polysilicon material for both the floating gate and control gate layers, allowing the same deposition and doping processes to be used for both gates. The stacked structure utilizes standard semiconductor fabrication techniques including sequential polysilicon deposition, dielectric layer formation, and photolithographic patterning. This universality of materials and processes enables the high-density stacked architecture to be manufactured using adapted conventional processes rather than requiring entirely new manufacturing capabilities.
Data Source
AI summary
A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant. The select device is activated by applying voltage to the second portion of first polysilicon layer.