Stack-Gate Layout with Threshold Zoning for Output Impedance
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Solution Overview
Problem
The design of FET cascode and stack-gate circuits faces trade-offs between output headroom and power consumption or layout area, and there is a need for reduced circuit parameter variations in serially connected transistors, particularly in current mirror circuits, where output impedance and threshold voltage consistency are crucial.
Innovation Solution
The stack-gate circuit design involves connecting the semiconductor channels of multiple transistors in series with collectively biased gates, using a layout that partitions the active zone into regions with varying threshold voltages to minimize impedance variations and improve output impedance, while maintaining efficient power usage and layout optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FET cascode and stack-gate circuits are used, then output impedance is improved, but output headroom and power consumption or layout area face trade-offs
Solution Approach 1:
The active zone is partitioned into multiple regions (first active region, second active region, third active region) with different threshold voltages. This segmentation allows each region to contribute differently to the overall circuit performance, enabling improved output impedance while managing layout area through spatial distribution of functional zones.
Solution Approach 2:
Different regions of the active zone are assigned different threshold voltage characteristics (first threshold voltage, second threshold voltage, third threshold voltage) to create local quality variations. This allows optimization of specific circuit parameters in different areas, achieving improved output impedance in critical regions while controlling overall layout area.
2Reliability
If transistors are serially connected to improve output impedance, then circuit parameter variations increase
Solution Approach 1:
The patent applies local quality by creating distinct active regions with different threshold voltages. The first active region has a first threshold voltage, the second active region has a second threshold voltage, and the third active region has a third threshold voltage. This spatial variation in threshold voltage characteristics allows serially connected transistors to maintain consistent parameters by distributing them across regions with compensating characteristics, thereby reducing overall parameter variations while preserving high output impedance.
Data Source
AI summary
A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.