Stack Type Memory Device 3D Architecture

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Solution Overview

Problem

Existing resistive memory devices face challenges in increasing integration density due to word line instability and limited area capacity, particularly in phase-change memory devices where narrow word lines lead to increased resistance and voltage instability.

Innovation Solution

A stack type memory device is designed with a semiconductor substrate, stacked active regions, gate electrodes surrounding the active layers, bit lines connected to drains, resistive device layers connected to sources, and a common source line, enabling a three-dimensional structure that improves integration density and prevents word line bouncing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the word line linewidth is narrowed to reduce integration density, then the integration density is improved, but the word line resistance increases causing word line bouncing and voltage instability

Engineering Contradiction:
Improveintegration densityVSAvoidword line voltage stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a planar two-dimensional layout to a three-dimensional stack type architecture. Multiple bit lines are stacked vertically above the semiconductor substrate, with memory cells formed at different heights. This vertical stacking enables higher integration density without requiring narrower word lines, thereby maintaining word line voltage stability while achieving increased capacity in a limited area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the area capacity is increased in a limited area, then the integration density is improved, but the device complexity increases

Engineering Contradiction:
Improvearea capacityVSAvoidstructure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory device is segmented into multiple stacked layers, with each layer containing bit lines, active regions, and memory cells at specific heights. The bit lines are divided into first bit lines and second bit lines at different vertical levels, allowing independent addressing and control. This segmentation enables high area capacity while managing complexity through modular layering and systematic interconnection.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stack type memory device enhances integration density and stabilizes word line voltage, allowing for higher capacity and lower power consumption in a limited area, addressing the limitations of existing resistive memory devices.

Implementation Method 1

the resistive memory device stores data '0' or '1' according to a state of the resistive device

Methodology Applied
Scientific EffectResistive switching: Electrical Resistance

Data Source

PatentUS9245588B2Stack type semiconductor memory device
Publication Date: 2016.01.26 SK HYNIX INC
  • US9245588B2 patent drawing
  • US9245588B2 patent drawing
  • US9245588B2 patent drawing

AI summary

A stack type memory device includes a semiconductor substrate; a plurality of bit lines arranged and stacked on the semiconductor substrate; a plurality of word lines formed on the plurality of bit lines; a plurality of interconnection units, each extending from a respective word line toward a respective one of the plurality of bit lines; and a plurality of memory cells connected between the plurality of bit lines and the interconnection units extending from the plurality of word lines, respectively.