Stack Memory Packet Communication via Segmented Lanes
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Solution Overview
Problem
Existing stack memory systems face challenges in achieving high-speed data transmission and efficient communication due to the complexity of designing physical interfaces that support high bandwidth and energy efficiency.
Innovation Solution
The proposed stack memory device incorporates a command control circuit that latches commands and addresses synchronously with a clock signal to generate latch commands and addresses, which are then decoded and encoded to produce row and column control signals. These signals are transmitted through separate interfaces to a core control circuit, enabling efficient control of internal operations on the core chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a parallel data bus is used for communication, then data transmission capacity is sufficient, but device complexity and energy consumption increase
Solution Approach 1:
The patent segments the communication interface into multiple independent lanes, each capable of transmitting data independently. This allows the system to achieve high data transmission capacity through parallel lanes while keeping each individual lane simple in design, thus resolving the contradiction between transmission capacity and interface complexity
Solution Approach 2:
The patent transitions from a traditional single-bus architecture to a multi-lane parallel architecture, adding spatial dimensionality to the data transmission path. This dimensional change enables scalable bandwidth increase without proportionally increasing the complexity of each transmission path
2Quantity of substance
If a parallel data bus is used for communication, then data transmission capacity is sufficient, but energy efficiency deteriorates
Solution Approach 1:
By segmenting the data transmission into multiple independent lanes, the system can activate only the necessary number of lanes based on current bandwidth requirements, reducing energy consumption when full bandwidth is not needed while maintaining the capability for high-capacity transmission when required
Solution Approach 2:
The patent implements dynamic lane activation and deactivation capabilities, allowing the communication interface to adapt its resource usage to actual workload demands, thereby optimizing energy efficiency while preserving high data transmission capacity availability
3Productivity
If high-speed data transmission is implemented, then bandwidth is improved, but signal integrity and communication reliability worsen
Solution Approach 1:
The patent introduces intermediary components including differential signaling pairs, equalization circuits, and error detection/correction mechanisms that mediate between the high-speed data sources and destinations, maintaining signal integrity and communication reliability despite high transmission speeds
Solution Approach 2:
The patent implements feedback mechanisms including acknowledgment signals, error detection and correction protocols, and retransmission capabilities that ensure reliable communication by continuously monitoring and correcting transmission errors that occur at high speeds
Data Source
AI summary
A stack memory device includes a command control circuit configured to latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address, decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface, and encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface, and a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip.