Stack Package Chip Selection via Voltage Dropping Units
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In stack packages with through-silicon vias, chip selection is hindered by identical vertical positions of chip selection pads, leading to increased processing costs and structural reliability issues due to wire bonding, which complicates the administration of chip selection processes.
Innovation Solution
A stack package configuration where first and second voltage dropping units, connected by separate lines with opposite current flow directions, generate signals for chip selection through diodes and logic gates, allowing for efficient chip selection without the need for redistribution layers or excessive wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If redistribution layers are formed to connect chip selection pads at different vertical positions, then chip selection becomes possible, but processing costs increase and process administration becomes difficult
Solution Approach 1:
The patent transitions from horizontal redistribution layers to vertical through-silicon via connections. By utilizing the vertical dimension through TSVs, chip selection pads can be connected across different chips without requiring complex planar redistribution patterns, thus simplifying the overall structure while maintaining selection capability.
Solution Approach 2:
The through-silicon vias serve multiple functions: they provide electrical connections for power/ground and simultaneously enable chip selection signaling. This multi-functionality eliminates the need for separate redistribution layers dedicated solely to chip selection, reducing process complexity.
2Ease of operation
If wire bonding is used to connect chip selection pads, then chip selection signals can be applied, but package thickness increases and signal delay occurs
Solution Approach 1:
The patent extracts the chip selection signaling function from the wire bonding process and integrates it directly into the through-silicon via structure. By taking out the need for separate wire bonds for selection signals, the package thickness is reduced and signal paths are shortened.
Solution Approach 2:
The patent merges the chip selection signal transmission path with the existing through-silicon via structure. By combining multiple functions (power/ground connection and selection signaling) into the same vertical pathway, wire bonding is eliminated and package thickness is reduced.
3Ease of operation
If wire bonding is used for chip selection, then signals can reach the chips, but structural reliability degrades
Solution Approach 1:
The patent combines chip selection signaling with the robust through-silicon via structure, eliminating fragile wire bonds. By merging the selection function into the mechanically stronger TSV infrastructure, both reliability and functionality are improved.
4Productivity
If through-silicon vias are used to stack chips, then high density and high performance are achieved, but chip selection becomes difficult due to identical vertical positions of selection pads
Solution Approach 1:
The patent introduces through-silicon vias as intermediary structures that extend vertically through multiple chips. These TSVs act as mediators that can carry selection signals from a single pad location on one chip to corresponding pad locations on other chips, enabling selection despite identical vertical pad positions.
Solution Approach 2:
The through-silicon vias perform multiple functions simultaneously: they provide power/ground connections and serve as pathways for chip selection signals. This multi-functionality enables chip selection capability without requiring additional structures that would compromise the high-density stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies chip selection operations, reduces package thickness, and enhances structural reliability by eliminating the need for redistribution layers and wire bonding, while maintaining high performance and miniaturization.
Implementation Method 1
first voltage dropping units respectively provided in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively provided in the plurality of chips the second dropping units are electrically coupled by a second line
Data Source
AI summary
A stack package having a plurality of stacked chips includes first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively.