Stack Package Data Transmission via Flag Signal Switching

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Solution Overview

Problem

Multi-channel stack packages face challenges in reducing size while maintaining high data storage capacity and operation speed due to the increased number of signal pads and transmission means, leading to larger semiconductor packages.

Innovation Solution

The implementation of a stack package configuration with multiple semiconductor chips, each equipped with data I/O pads, flag pads, and buffers, including exclusive NOR gates and switching portions, allows for selective data transmission based on flag signals and power voltage levels, enabling efficient switching operations and reducing the need for multiple signal pads and transmission means.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple channel groups are used to increase operation speed, then data transmission speed is improved, but the number of signal pads and transmission means increases leading to larger package size

Engineering Contradiction:
Improvedata transmission speedVSAvoidpackage size
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The patent merges multiple channel groups into a single integrated stack package structure. Multiple semiconductor chips are vertically stacked and interconnected through wire bonds, combining what would traditionally require separate packages into one compact unit. This merging approach maintains multi-channel data transmission capabilities while significantly reducing the overall package footprint compared to using multiple separate packages.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a planar two-dimensional arrangement of chips to a three-dimensional vertical stacking configuration. By stacking chips vertically and using wire bonds to interconnect them, the design exploits the third dimension (height/vertical space) to accommodate multiple channel groups without increasing the lateral package footprint, thus maintaining high transmission speed while minimizing package size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If the number of channel groups increases to meet fast operation requirements, then operation speed is improved, but device complexity increases due to more signal pads and transmission means

Engineering Contradiction:
Improveoperation speedVSAvoidnumber of signal pads and transmission means
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the multi-channel data transmission function across multiple semiconductor chips stacked vertically. Each chip can handle specific channel groups, and the segmentation is managed through controlled switching mechanisms (such as XOR gates and switches) that route data through appropriate channels. This segmentation allows high-speed multi-channel operation while keeping each individual chip and its associated signal pads relatively simple.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic switching mechanisms that can selectively activate or deactivate different data transmission paths based on operational requirements. The switches and XOR gates enable dynamic routing of data signals through different channel groups, allowing the system to adaptively manage complexity by only activating necessary transmission paths during operation, thereby reducing the effective complexity despite having multiple channel groups available.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9318420B2Chip stack packages, system in packages including the same, and methods of operating the same
Publication Date: 2016.04.19 SK HYNIX INC
  • US9318420B2 patent drawing
  • US9318420B2 patent drawing
  • US9318420B2 patent drawing

AI summary

A stack package including a first semiconductor chip and second semiconductor chip, the first semiconductor chip including first data I/O pads for transmitting data I/O signals, a first flag pad for receiving a flag signal, and a first buffer for controlling a switching operation between the first data I/O pads and an internal circuit of the first semiconductor chip. The second semiconductor chip includes second data I/O pads for transmitting the data I/O signals, a second flag pad for receiving the flag signal, and a second buffer for controlling a switching operation between the second data I/O pads and an internal circuit of the second semiconductor chip. The first data I/O pads are electrically connected to respective ones of the second data I/O pads through first wires, and the first flag pad is electrically connected to the second flag pad through a second wire. Related methods are also provided.