Stack Package Guard Rings for Thermal Stress Relief

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Solution Overview

Problem

Conventional stack packages using through-via interconnection plugs experience cracks and disconnections at joint regions due to thermal expansion and contraction, leading to reduced joint and device reliability during thermal cycle tests.

Innovation Solution

The implementation of guard rings surrounding through-via interconnection plugs to absorb thermally-induced stresses, ensuring electrical insulation and reducing stress concentration at joint regions, thereby preventing cracks and disconnections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-via interconnection plugs are used to connect stacked chips, then electrical connection between chips is achieved, but cracks and disconnections occur at joint regions due to thermal expansion and contraction

Engineering Contradiction:
Improvejoint reliabilityVSAvoidthermal stress
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An insulating layer is introduced as an intermediary material between the through-via interconnection plug and the chip substrate. This insulating layer acts as a stress buffer that absorbs and distributes thermal expansion stresses, preventing direct stress transmission that causes cracks and disconnections at the joint regions between chips.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating layer is formed within the through-hole before the metal plug is deposited, creating a pre-positioned stress-absorbing structure. This beforehand cushioning approach ensures that thermal stresses are mitigated before they can propagate to cause damage during thermal cycling operations.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If metal connection plugs are formed by electro-plating, then electrical conductivity is achieved, but stress concentration occurs at the plug-chip interface

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidstress concentration
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The insulating layer serves as a mediator between the metal connection plug and the chip substrate, decoupling the stress transmission path while maintaining electrical connection functionality. This intermediary structure prevents stress concentration at the plug-chip interface by distributing thermal stresses throughout the insulating material.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The through-via structure becomes a composite system combining the metal plug (for electrical conductivity) and the insulating layer (for stress management). This composite material approach allows simultaneous achievement of electrical connection reliability and stress reduction by leveraging the complementary properties of different materials.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of guard rings enhances the reliability of solder joints and overall package reliability by preventing stress-induced failures at joint regions between chips, improving thermal cycle reliability.

Implementation Method 1

The connection plug made of a metal is formed by electro-plating

Methodology Applied
Scientific EffectElectro-plating: Electroplating

Implementation Method 2

A seed metal layer made of a conductive metal is deposited over the oxide layer through CVD or PVD

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

A seed metal layer made of a conductive metal is deposited over the oxide layer through CVD or PVD

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 4

the backside of the wafer is back-grinded

Methodology Applied
Scientific EffectAbrasion: Abrasion

Data Source

PatentUS7871925B2Stack package and method for manufacturing the same
Publication Date: 2011.01.18 SK HYNIX INC
  • US7871925B2 patent drawing
  • US7871925B2 patent drawing
  • US7871925B2 patent drawing

AI summary

A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.