Stack Package Interposer Bridge for Compact Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor package technologies face challenges in reducing the size of semiconductor packages while maintaining high memory capacity, as traditional two-dimensional chip arrangements limit the efficient use of space and interconnectivity.
Innovation Solution
The proposed stack package design incorporates a lower semiconductor chip, an interposer bridge with through vias, and an upper semiconductor chip stacked vertically, with specific redistribution layer patterns and pad arrangements to enhance electrical connectivity and reduce package size, allowing for efficient power and signal delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of semiconductor chips are two-dimensionally disposed on the same plane, then the memory capacity is increased, but the planar area and package size increase
Solution Approach 1:
The patent transitions from two-dimensional chip arrangement to three-dimensional stacking by vertically stacking multiple semiconductor chips. The upper semiconductor chip is positioned above the lower semiconductor chip, utilizing the vertical dimension to increase memory capacity without proportionally increasing the planar footprint of the package.
Solution Approach 2:
The patent implements a nested structure where the upper semiconductor chip is positioned within the vertical space above the lower semiconductor chip. The chips are arranged in a stacked configuration where each chip occupies a different vertical level, creating a compact nested arrangement that maximizes space utilization.
2Area of stationary object
If semiconductor chips are vertically stacked to reduce package size, then the planar area is reduced, but interconnectivity and electrical connection complexity increase
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between the lower and upper semiconductor chips. The interposer substrate provides a platform for forming connection structures (such as through-silicon vias or bump electrodes) that electrically connect the chips, thereby managing the complexity of vertical interconnections and simplifying the bonding process.
Solution Approach 2:
The patent divides the electrical connection system into separate functional components: the lower chip, the interposer substrate, and the upper chip. Each component has dedicated connection regions and electrodes that are separately formed and then assembled, allowing for modular manufacturing and reducing the overall complexity of creating direct chip-to-chip connections.
3Reliability
If redistribution layer patterns are extended to overlap with through vias, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the connection structures (through vias or bump electrodes) on the interposer substrate before assembling the upper semiconductor chip. This preliminary formation of connection elements ensures proper alignment and electrical connectivity, as the connection structures are already positioned and prepared to receive the chip's electrodes, reducing the need for high-precision alignment during final assembly.
Data Source
AI summary
A stack package includes a lower semiconductor chip disposed on a package substrate, an interposer bridge including through vias, and an upper semiconductor chip. The upper semiconductor chip has a first edge and a second edge which are opposite to each other. The upper semiconductor chip includes a first region, a third region and a connection region which are located between the first and second edges. The upper semiconductor chip also includes a redistributed layer pattern that connects pads disposed on the first and third regions to each other. The redistributed layer pattern extends onto the connection region.