Stack Package Interposer Vertical Signal Routing

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Solution Overview

Problem

The existing manufacturing of semiconductor stack packages is costly and performance is compromised due to the need for horizontal signal lines in interposers, especially when combining Ajinomoto build-up film (ABF) and high-density interconnection (HDI) packages with different pad pitches.

Innovation Solution

A stack package design that includes ABF and HDI packages with different pad pitches, where the interposer has pads with the same pitch as the ABF package, eliminating the need for horizontal signal lines by using vertical signal lines for connection, thereby reducing manufacturing costs and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If an interposer is applied to an ABF package to create a stack package with large area, then the manufacturing cost increases significantly

Engineering Contradiction:
Improvestack package areaVSAvoidmanufacturing cost
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The interposer is divided into multiple layers: a first interposer layer with first pads matching the ABF package pitch, and a second interposer layer with second pads matching the HDI package pitch. This segmentation allows each layer to independently interface with packages of different pitches without requiring expensive customization of the entire interposer structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-plane interposer design to a multi-layer vertical structure. The first interposer layer connects to the ABF package above, while the second interposer layer connects to the HDI package below, utilizing the vertical dimension to accommodate different pitch requirements without increasing horizontal area or manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If an interposer with fine pitch is used to connect to HDI package pads, then horizontal signal lines are required which increase resistance and deteriorate performance

Engineering Contradiction:
Improveelectrical connection performanceVSAvoidresistance increase
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Instead of routing signals horizontally across the interposer from one edge to another, the patent inverts the connection approach by using vertical signal lines that extend downward from the second pads of the second interposer layer directly to the HDI package pads. This vertical routing eliminates the need for long horizontal signal lines and their associated resistance problems.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent extracts and eliminates the horizontal signal line component from the interposer design. By directly connecting the second pads to the HDI package pads through vertical connections, the design removes the problematic horizontal signal line element that caused resistance increase, keeping only the essential vertical interconnection function.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11205614B2Stack packages
Publication Date: 2021.12.21 SAMSUNG ELECTRONICS CO LTD
  • US11205614B2 patent drawing
  • US11205614B2 patent drawing
  • US11205614B2 patent drawing

AI summary

A stack package may include a first substrate package, a second substrate package, an interposer and at least one semiconductor chip. The first substrate package may include a plurality of first pads isolated from direct contact with each other by a first pitch. The second substrate package may be under the first substrate package. The second substrate package may include a plurality of second pads isolated from direct contact with each other by a second pitch. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads isolated from direct contact with each other by a third pitch. The semiconductor chip may be arranged above the interposer.