Stack Package Mirrored Step Configuration
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Solution Overview
Problem
Conventional stack packaging techniques face challenges in miniaturization and signal mismatch due to increased size and wire bonding length as the number of semiconductor chips increases, leading to inefficiencies in mounting reliability and electrical signal alignment.
Innovation Solution
A stack package configuration featuring a substrate with mirrored step-like stacking of semiconductor chips and connection members, such as anisotropic conductive films or wires, to maintain compact size and ensure uniform signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires are used to electrically connect stacked semiconductor chips to substrate, then electrical connection is achieved, but the transverse and longitudinal sizes of the package must be increased
Solution Approach 1:
The patent transitions from planar wire routing to three-dimensional vertical stacking, where semiconductor chips are stacked in the thickness direction and electrically connected through vertical vias and conductive structures. This dimensional change allows electrical connections without increasing the package's transverse footprint, resolving the contradiction between connection reliability and package compactness.
Solution Approach 2:
The patent implements nested structures where multiple semiconductor chips are stacked within a compact package volume, with lower chips containing connection members that extend upward to connect with upper chips. This nesting approach maximizes space utilization and achieves electrical connectivity without expanding the package's external dimensions.
2Quantity of substance
If the number of stacked semiconductor chips is increased, then high capacity is achieved, but the wire bonding length increases causing signal mismatch
Solution Approach 1:
The patent arranges semiconductor chips in vertical stacks along the thickness direction, creating multiple layers of integrated circuits. This three-dimensional configuration allows increased chip capacity while maintaining controlled signal path lengths through vertical interconnections, preventing the signal mismatch that would occur with extended horizontal wire routing.
Solution Approach 2:
The patent divides the package into multiple stacked chip layers, each segment handling specific functions. By segmenting the system vertically, signal paths are localized within each chip layer and connected through controlled vias, ensuring uniform signal lengths and preventing mismatch even as the total number of chips increases.
3Ease of manufacture
If step-like stacking procedure is used for single bonding pad type chips, then stacking is achieved, but the transverse size of the package significantly increases
Solution Approach 1:
The patent employs vertical stacking in the thickness direction rather than horizontal step-like arrangement. Connection members extend vertically from lower chips to upper chips, enabling the stacking procedure to be implemented without increasing the package's transverse dimensions, thus resolving the contradiction between manufacturability and compactness.
Data Source
AI summary
A stack package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, a lower stack group, an upper stack group, and connection members. The lower stack group is attached to the upper surface of the substrate and includes at least two semiconductor chips which are stacked in a face-up type to form on or more steps. The upper stack group is disposed over the lower stack group and includes at least two semiconductor chips which are stacked in a face-down type in such a way as to form one or more steps whose direction mirrors the direction of the at least one step of the lower stack group. The connection members electrically connect the semiconductor chips of the lower and upper stack groups to the substrate.