Stack Package With Molding Part For Structural Stability

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Solution Overview

Problem

Stacking semiconductor chips with different sizes poses structural instability issues, making it challenging to achieve a stable stack package, especially when the upper chip is larger than the lower chip.

Innovation Solution

A stack package design that includes a first semiconductor chip with through-electrodes, multiple larger second semiconductor chips stacked on it, and a molding part that surrounds the first chip to match or exceed the size of the larger chips, ensuring structural stability, along with additional features like encapsulation members, redistribution lines, and underfills to secure connections and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If larger second semiconductor chips are stacked on a smaller first semiconductor chip, then the capacity and integration of the stack package is improved, but structural stability deteriorates

Engineering Contradiction:
Improvechip capacityVSAvoidstructural stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

A molding part is introduced as an intermediary component between the first and second semiconductor chips. This molding part has a size that is equal to or larger than the second semiconductor chip, providing a stable base structure that supports the larger chip while being attached to the smaller first chip, thus resolving the structural instability issue

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The solution transitions from a two-dimensional planar stacking problem to a three-dimensional structure by introducing the molding part that extends laterally beyond the first chip's boundaries. This dimensional extension provides the necessary support area for stabilizing the larger second chip

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If through-electrodes are used to connect stacked chips, then I/O pad bonding precision and signal transmission speed are improved, but manufacturing complexity increases

Engineering Contradiction:
ImproveI/O pad bonding precisionVSAvoidmanufacturing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Through-electrodes are pre-formed in the first semiconductor chip before the stacking process. This preliminary formation of connection structures simplifies the subsequent assembly process and ensures precise alignment and bonding of I/O pads during chip stacking

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If chips of different sizes are stacked, then design flexibility and adaptability are improved, but structural stability and reliability deteriorate

Engineering Contradiction:
Improvedesign flexibilityVSAvoidstack reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The molding part is designed with localized properties where its size is specifically matched to the second semiconductor chip rather than the first chip. This local adaptation allows the structure to accommodate different chip size combinations while maintaining stability, as the molding part provides the appropriate support geometry for each specific chip configuration

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8110910B2Stack package
Publication Date: 2012.02.07 SK HYNIX INC
  • US8110910B2 patent drawing
  • US8110910B2 patent drawing
  • US8110910B2 patent drawing

AI summary

A stack package includes a first semiconductor chip possessing a first size and one or more second semiconductor chips possessing a second size greater than the first size. The first semiconductor chip has a first surface on which bonding pads are disposed, a second surface which faces away from the first surface, and first through-electrodes which pass through the first surface and the second surface. The one or more second semiconductor chips are stacked on the second surface of the first semiconductor chip and have second through-electrodes which are electrically connected to the first through-electrodes. A molding part abuts one or more side surfaces of the first semiconductor chip such that a total size including the first size and a size of the molding part is equal to or greater than the second size.