Stack Package With Penetrating Bumps For Reduced Interconnection Length
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Solution Overview
Problem
The electronics industry faces challenges in creating compact, high-performance semiconductor packages with reduced interconnection lengths and improved electrical characteristics, which existing stack packages struggle to achieve effectively.
Innovation Solution
The proposed solution involves a stack package configuration where first and second chips are vertically stacked, with through electrodes penetrating each chip, and bumps on the chips' surfaces that penetrate the insulation layer to electrically connect, using conductive materials with low melting points and insulation layers like silicon oxide to enhance bonding and reduce package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through electrodes are used to vertically align and electrically couple semiconductor chips in a stack package, then interconnection length is reduced and electrical characteristics are improved, but manufacturing complexity increases due to the need for precise alignment and through electrode formation
Solution Approach 1:
The patent applies preliminary action by pre-forming protrusions on the first chip and recesses on the second chip before stacking. This preliminary structuring enables automatic alignment during the stacking process, eliminating the need for complex post-assembly alignment procedures and reducing manufacturing complexity while maintaining the electrical coupling benefits of through electrodes.
Solution Approach 2:
The patent introduces an insulation layer as an intermediary element between the through electrodes of different chips. This insulation layer with protrusions and recesses acts as a mediator that facilitates alignment and electrical coupling while managing the complexity of direct through electrode integration, allowing chips to be vertically stacked with improved electrical characteristics without excessive manufacturing difficulty.
2Volume of moving object
If multiple semiconductor chips are stacked vertically to create compact packages, then package size is reduced, but bonding reliability between chips becomes more critical and difficult to maintain
Solution Approach 1:
The patent applies local quality by creating localized protrusions and recesses at specific bonding interfaces between chips. Instead of requiring uniform bonding across entire chip surfaces, the localized structural features concentrate bonding reliability at critical points, enabling compact vertical stacking while maintaining reliable electrical and mechanical connections between individual chip layers.
3Length of moving object
If through electrodes penetrate chip bodies to enable vertical electrical coupling, then interconnection length is reduced, but thermal expansion differences between materials increase stress on the package structure
Solution Approach 1:
The insulation layer acts as a intermediary that buffers thermal expansion differences between the through electrodes and chip substrates. By positioning this layer between dissimilar materials with different thermal expansion coefficients, the patent reduces stress accumulation during temperature cycling while maintaining the short interconnection length benefits of vertical through electrode coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces interconnection lengths, improves electrical characteristics, and enhances bonding coherence between chips, resulting in compact, high-performance semiconductor packages with improved reliability and reduced thermal expansion differences.
Implementation Method 1
using conductive materials with low melting points and insulation layers like silicon oxide to enhance bonding and reduce package thickness
Data Source
AI summary
Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip.