Stack Package Sidewall Interconnectors for Thin Profile
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Solution Overview
Problem
The challenge lies in developing stack packages that are increasingly smaller and thinner to meet the demands of multi-functional and large capacitive semiconductor packages, while maintaining electrical connectivity and minimizing thickness without the need for additional spacers.
Innovation Solution
The solution involves stacking semiconductor chips with strategically aligned connectors and interconnectors, where each chip has connectors on its edges, and sidewall interconnectors extend along the sides of the chips to cover and connect these connectors, allowing for the placement of metal wires without contacting the bottom surface, thus eliminating the need for spacers and minimizing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional spacers are used to maintain electrical connectivity between stacked chips, then electrical connection stability is improved, but package thickness increases
Solution Approach 1:
The patent introduces sidewall interconnectors as intermediary elements that extend along the sidewalls of stacked chips to provide electrical connectivity. These interconnectors act as mediators between connection terminals on different chips, eliminating the need for spacers while maintaining stable electrical connections. The sidewall interconnectors are positioned on the lateral surfaces of chips, allowing vertical stacking without increasing horizontal spacing requirements.
Solution Approach 2:
The patent transitions from horizontal spacer-based connectivity to vertical sidewall-based connectivity. By placing interconnectors on the sidewalls of chips and extending them vertically along the stacking direction, the invention utilizes the vertical dimension for electrical connection rather than relying on horizontal spacers. This dimensional shift enables thinner package profiles while maintaining connection stability.
2Volume of moving object
If chip size is reduced to create smaller stack packages, then package size is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the electrical connection function into multiple components: connection terminals on chips, sidewall interconnectors extending from these terminals, and corresponding bonding pads on the substrate. This segmentation allows each component to be optimized independently, with connectors positioned at specific locations and interconnectors providing flexible routing paths, thereby reducing the cumulative precision requirements compared to direct single-point connections.
Solution Approach 2:
The patent changes the geometric parameters of the connection system by positioning connectors on the edges of chips rather than at center locations, and by extending interconnectors along sidewalls rather than using horizontal spacers. These parameter changes create more favorable alignment conditions and reduce the sensitivity to manufacturing variations, enabling smaller package sizes with acceptable precision requirements.
3Adaptability or versatility
If multiple chips are stacked to increase package functionality, then device capacity is improved, but package complexity increases
Solution Approach 1:
The patent creates a universal stacking architecture where the same sidewall interconnector structure can be used to connect multiple chips in series. The connection terminals, sidewall interconnectors, and bonding pads form a standardized interface that can be replicated across multiple stacking levels. This multi-functional design allows the same structural elements to serve both electrical connection and mechanical support functions, reducing the need for additional specialized components as chip count increases.
Data Source
AI summary
A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.