Stack Package Supporter for 3D Semiconductor Warpage Control

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Solution Overview

Problem

The challenge in semiconductor chip stack technologies is warpage caused by differences in thermal expansion coefficients between semiconductor chips and molding members, which affects the rigidity and stability of the stack package.

Innovation Solution

A stack package design that includes a supporter attached to the first semiconductor chip, spaced apart from the edge of the second semiconductor chip, with a molding member covering the upper surface to seal both chips, and a thermal interface material layer for heat dissipation, ensuring the supporter has a higher Young's modulus than the molding member but lower than the semiconductor chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If thin semiconductor chips are stacked to increase integration density, then the number of chips per package is increased, but warpage is caused due to difference in thermal expansion coefficients between the semiconductor chip and molding member

Engineering Contradiction:
Improveintegration densityVSAvoidwarpage
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

A supporter layer is introduced as an intermediary component between the semiconductor chip and the molding member. This supporter has a thermal expansion coefficient that is lower than that of the semiconductor chip, acting as a buffer to compensate for the differential thermal expansion between the chip and molding member, thereby preventing warpage while maintaining the thin-chip stacked structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The package structure employs a composite material system consisting of the semiconductor chip, supporter layer, and molding member with different thermal expansion properties. The supporter layer is specifically selected with a thermal expansion coefficient lower than the semiconductor chip to create a gradient structure that balances thermal stresses during temperature changes

Inventive Principle:
Principle #40Composite materials

2Stability of the object's composition

If a supporter is attached onto the first semiconductor chip to prevent warpage, then mechanical stability is improved, but the device structure becomes more complex

Engineering Contradiction:
Improvemechanical stabilityVSAvoidstructure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The supporter layer serves multiple functions simultaneously: it prevents warpage by compensating for thermal expansion differences, provides mechanical support to the thin semiconductor chip, and acts as a stress buffer during thermal cycling. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in structural complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively prevents warpage and enhances mechanical stability and heat dissipation, reducing thermal stress and improving the overall reliability of the semiconductor package.

Implementation Method 1

the supporter has a higher Young's modulus than the molding member but lower than the semiconductor chip

Methodology Applied
Scientific EffectElasticity: Elasticity

Implementation Method 2

a thermal interface material layer for heat dissipation

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 3

a molding member covering the upper surface to seal both chips

Methodology Applied
Scientific EffectPhysical containment: Physical Containment

Data Source

PatentUS8791562B2Stack package and semiconductor package including the same
Publication Date: 2014.07.29 SAMSUNG ELECTRONICS CO LTD
  • US8791562B2 patent drawing
  • US8791562B2 patent drawing
  • US8791562B2 patent drawing

AI summary

A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.