Stack Package TSV Interface Circuit Variable Voltage Error Prediction
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Solution Overview
Problem
Three-dimensional (3D) stack packages face challenges in increasing integration density and reducing size while addressing low transmission speeds and data bandwidth limitations due to the distance of controllers and package variables in memory chips.
Innovation Solution
A stack package design incorporating a first and second chip with an interconnecting unit and interface circuit unit, where the interface circuit unit is electrically coupled to through silicon via (TSV) and receives a variable voltage, enabling accurate prediction and improvement of errors caused by chip-level and TSV interface circuit unit interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory chips are arranged in a two-dimensional structure to increase integration degree, then the integration degree improves, but the capacity and size reduction are limited
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of memory chips to a three-dimensional stack package structure. Multiple memory chips are vertically stacked and interconnected through through-silicon-vias (TSVs), enabling increased integration density and capacity without proportionally increasing the package footprint. This dimensional change allows the system to achieve higher capacity while maintaining compact size.
2Quantity of substance
If the distance of controller on module is increased to accommodate more chips, then the capacity increases, but transmission speed decreases
Solution Approach 1:
By stacking memory chips vertically in three dimensions rather than arranging them horizontally, the patent reduces the average distance between controllers and memory arrays. This vertical integration maintains short signal paths despite increased capacity, preserving high transmission speeds even as more chips are accommodated in the package.
Solution Approach 2:
The patent introduces high-speed interconnect structures, specifically through-silicon-vias (TSVs) and advanced bonding techniques, as intermediaries to enable fast data transmission between stacked chips. These intermediary connection structures minimize signal degradation and maintain high bandwidth across the three-dimensional chip interconnections.
3Adaptability or versatility
If TSV technique is used to form holes and electrodes for communication between chips, then the three-dimensional structure is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process by pre-forming TSV holes and electrodes in each memory chip before stacking. This allows the complex TSV structures to be created using standard semiconductor fabrication processes on individual chips, which are then assembled into the three-dimensional package. This approach simplifies the overall manufacturing by breaking down the complex 3D TSV formation into manageable sequential steps rather than attempting to create the entire 3D structure in one process.
Data Source
AI summary
A stack package may include a first chip, a second chip, a through silicon via (TSV) and an interface circuit unit. The first chip may include a first internal circuit unit driven by an internal voltage. The second chip may be stacked over the first chip. The second chip may include a second internal circuit unit driven by the internal voltage. The TSV may be electrically coupled between the first chip and the second chip. The interface circuit unit may be arranged in the first chip and the second chip. The interface circuit unit may be coupled to the TSV. A portion of the interface circuit unit may be received a variable voltage different from the internal voltage as a driving voltage.