Stack Package Using Through Silicon Vias and Redistribution Lines
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Solution Overview
Problem
Conventional stack packages face challenges in stacking same-size semiconductor chips without shock-absorbing tapes and in applying to high-speed products due to the use of metal wires, which also increase the package size.
Innovation Solution
The use of through silicon vias (TSVs) and re-distribution lines, along with solder balls, to form electrical and physical connections between semiconductor chips and a printed circuit board, allowing for same-size chip stacking and reduced package size by eliminating the need for metal wires and shock-absorbing tapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wires are used to connect bonding pads to circuit patterns, then electrical connections can be established, but the package size increases due to wire loops
Solution Approach 1:
The patent extracts and eliminates the metal wire interconnect structure from the package. Instead of using wire bonds that create loops and increase package size, the invention uses direct PCB trace connections and surface-mounted components to establish electrical connections, thereby removing the source of the volume problem while maintaining electrical connectivity
Solution Approach 2:
The patent transitions from three-dimensional wire loop structures to two-dimensional PCB trace routing. By flattening the interconnect path onto the PCB surface and using surface-mounted components, the invention eliminates the vertical wire loops that consume package volume, effectively moving the connection strategy to a different dimensional approach
2Reliability
If bonding pads are formed on peripheral portions and connected by metal wires, then electrical connections are achieved, but same-size semiconductor chips cannot be stacked without shock-absorbing tapes
Solution Approach 1:
The patent makes the PCB serve multiple functions: it acts as both the electrical interconnection substrate and the mechanical support structure for stacking chips. The PCB's rigid structure provides shock absorption without requiring additional shock-absorbing tapes, while its circuit traces provide electrical connections, eliminating the need for separate wire bonds and complex stacking arrangements
Solution Approach 2:
The patent merges the functions of wire bonding, mechanical support, and shock absorption into the PCB structure itself. By integrating these functions into a single substrate, the invention eliminates the need for separate components like shock-absorbing tapes and metal wires, thereby simplifying the stacking structure and enabling same-size chip stacking
3Reliability
If metal wires are used for electrical connections, then bonding pads can be connected to circuit patterns, but the application to high-speed products becomes difficult
Solution Approach 1:
The patent replaces the mechanical wire bond system with an electrical trace-based system on the PCB. This substitution eliminates the inductance and resistance issues associated with wire bonds, enabling better performance in high-speed applications while maintaining reliable electrical connections between components
Data Source
AI summary
A stack package includes a printed circuit board; at least two semiconductor chips stacked on the printed circuit board, each having first re-distribution lines formed on the upper surface thereof and connected to bonding pads, through silicon vias which are formed therethrough and connected to the first re-distribution lines, and second re-distribution lines formed on the lower surface thereof and connected to the through silicon vias; first and second solder balls interposed between the first and second re-distribution lines which face each other and between the first re-distribution lines of the lowermost semiconductor chip and electrode terminals of the printed circuit board; a molding material for molding the upper surface of the printed circuit board including the stacked semiconductor chips; and third solder balls attached to ball lands formed on the lower surface of the printed circuit board.