Stack Package Via-Hole Bump Connection for Signal Delay
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Solution Overview
Problem
Conventional stack packages face delays in electrical signal transmission due to increased electrical connection lengths between semiconductor chips, limiting their application in high-speed operations and resulting in larger package sizes.
Innovation Solution
A stack package design featuring via-holes and metal bumps with a trapezoidal sectional shape on the upper semiconductor chip, where the metal bumps from the lower chip are inserted into the via-holes of the upper chip, reducing electrical connection paths and using a bonding material for attachment, allowing direct contact between bonding pads and metal bumps for efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire rerouting processes or wire bonding processes are used to electrically connect upper and lower semiconductor chips, then electrical connection is achieved, but electrical connection length increases causing signal transmission delay
Solution Approach 1:
The patent extracts and eliminates the wire rerouting and wire bonding processes from the stack package manufacturing. Instead of using these intermediate connection methods, the invention directly connects bonding pads through vias and bumps, removing the harmful intermediate elements that caused increased connection length and signal delay.
Solution Approach 2:
The patent performs preliminary actions by pre-forming vias with openings that expose bonding pads, and pre-forming bumps on bonding pads before stacking. This preliminary preparation enables direct electrical connection upon stacking, eliminating the need for post-assembly wire routing and reducing overall connection length.
2Reliability
If conventional wire bonding processes are used for electrical connection, then connectivity is established, but package size increases
Solution Approach 1:
The patent removes the wire bonding process and associated wiring infrastructure from the package design. By using direct via-bump connections embedded within the chip structure, the solution eliminates the external wiring space requirements that contributed to increased package size.
Solution Approach 2:
The patent transitions from planar wire routing to vertical three-dimensional connection through vias and bumps. This dimensional change allows electrical connections to be made within the vertical stack rather than requiring lateral wire routing space, thereby reducing the overall package footprint.
Data Source
AI summary
A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.