Stack Pointer Prediction via Physical Register Mapping
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Solution Overview
Problem
The limited number of architectural registers in processors leads to delays when variables stored in memory need to be read back into registers, as the process of reading from memory introduces latency, particularly in situations with insufficient registers for multiple functions or during function calls.
Innovation Solution
A method is introduced to predict pointer values of variables stored in the stack by maintaining a data structure that maps physical registers to stack pointers and offsets, allowing architectural registers to be directly mapped to physical registers without the need for memory loads, thereby eliminating latency and enabling out-of-order execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If variables are stored in memory to free up architectural registers, then register availability is improved, but access latency increases due to memory reads
Solution Approach 1:
The patent performs preliminary actions by predicting stack pointer values and pre-loading variable values into physical registers before they are actually needed by instructions. The system anticipates future memory access requirements and prepares data in advance, eliminating latency when variables are needed.
Solution Approach 2:
The patent creates a cushioning effect by maintaining a buffer of pre-loaded values in physical registers. When stack pointer prediction indicates that variables will be needed, they are loaded into registers in advance, providing a cushion against future latency requirements and ensuring data availability without blocking instruction execution.
2Quantity of substance
If the number of architectural registers is increased, then register availability is improved, but instruction set complexity increases
Solution Approach 1:
The patent transitions from a single-dimensional register architecture to a multi-dimensional solution by introducing physical registers as a second layer beyond architectural registers. This dimensional extension allows the system to provide additional storage capacity without modifying the architectural register interface or instruction set, effectively adding space in a new dimension rather than expanding the existing structure.
Solution Approach 2:
The patent introduces physical registers as an intermediary layer between architectural registers and memory. This intermediary structure provides additional storage capacity while maintaining the existing architectural interface, allowing the system to overcome architectural register limitations without requiring changes to the instruction set or architectural interface.
3Speed
If variables are kept in architectural registers, then access speed is improved, but register availability decreases when functions are nested
Solution Approach 1:
The patent segments the register storage system into two distinct parts: architectural registers for frequently accessed variables requiring fast access, and physical registers for additional storage capacity. This segmentation allows variables to be distributed across different storage layers based on access patterns, maintaining fast access for critical variables while providing additional storage for nested function variables.
Solution Approach 2:
The patent adds a second dimensional layer of physical registers that exists parallel to the architectural register space. This dimensional addition provides extra storage capacity for nested function variables without interfering with the existing architectural register interface or access patterns, allowing both fast access and increased availability to coexist.
Data Source
AI summary
Methods of predicting stack pointer values of variables stored in a stack are described. When an instruction is seen which stores a variable in the stack in a position offset from the stack pointer, an entry is added to a data structure which identifies the physical register which currently stores the stack pointer, the physical register which stores the value of the variable and the offset value. Subsequently when an instruction to load a variable from the stack from a position which is identified by reference to the stack pointer is seen, the data structure is searched to see if there is a corresponding entry which includes the same offset and the same physical register storing the stack pointer as the load instruction. If a corresponding entry is found the architectural register in the load instruction is mapped to the physical register storing the value of the variable from the entry.