Stack Type Semiconductor Package Fine Pitch Alignment
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Solution Overview
Problem
Stack type semiconductor packages face difficulties in stable stacking due to fine pitches of external connection terminals, making it challenging to align and connect upper semiconductor packages with lower ones.
Innovation Solution
The solution involves a stack type semiconductor package design with a lower package featuring a circuit board, semiconductor chip, via-pads, and an encapsulation layer with via-holes, and an upper package with internal connection terminals, along with redistribution layers that connect via-pads to internal terminals, facilitating easy stacking and electrical connection despite fine pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitches of external connection terminals are reduced to achieve finer pitches, then the density of connection terminals increases, but it becomes difficult to stack the upper semiconductor package on the lower semiconductor package
Solution Approach 1:
The patent introduces an intermediary structure (alignment mark or guide structure) between the upper and lower semiconductor packages to facilitate precise alignment during stacking. This intermediary element enables accurate positioning even when the connection terminals have fine pitches that would otherwise be difficult to align manually or with standard positioning methods.
Solution Approach 2:
The patent implements preliminary alignment marks or guide structures on the package substrates before the actual stacking process. These pre-formed alignment features allow for precise positioning to be established in advance, enabling the subsequent stacking of fine-pitch terminals to proceed accurately without requiring complex real-time adjustment mechanisms.
2Productivity
If the pitches of external connection terminals are reduced, then more connections can be made in a given area, but the difficulty of alignment and stacking increases
Solution Approach 1:
The alignment mark structure serves as a mediator that translates the fine-pitch terminal positions into easily detectable and alignable reference points. By providing these intermediary alignment features, the system achieves both high connection density through fine pitches and high alignment precision through the larger, more easily positioned alignment marks.
Solution Approach 2:
The patent segments the alignment function from the connection function by providing separate alignment marks distinct from the connection terminals themselves. This segmentation allows the connection terminals to maintain fine pitches for high density while the alignment marks can be larger and more spaced out for easier and more precise alignment during manufacturing.
3Area of stationary object
If fine pitch terminals are used to increase connection density, then the package size can be reduced, but the stacking process becomes more difficult
Solution Approach 1:
The patent forms alignment marks and guide structures on the package substrates during the manufacturing process, before the stacking operation. This preliminary action ensures that when fine-pitch terminals are used to minimize package footprint, the stacking process remains easy by providing pre-established alignment references that guide the positioning of upper packages relative to lower packages.
Solution Approach 2:
The alignment marks act as intermediary reference features that enable the stacking process to proceed easily even when fine-pitch terminals are used. These intermediary markers provide a coarser alignment scale that is easier to work with during manufacturing, while the fine-pitch terminals maintain the compact package footprint.
Data Source
AI summary
A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.