Stack Semiconductor Package Wiring Layout
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Solution Overview
Problem
In Package-On-Package (POP) semiconductor devices, the complex wiring layout between semiconductor chips leads to deteriorated routability and signal connection performance, making it challenging to achieve high-speed and compact electronic products.
Innovation Solution
A stack semiconductor package design is implemented, where a first semiconductor package with chip pads along its side portion is stacked with a second package containing sub-chips arranged side by side, with connection pads on both packages to reduce and simplify wiring paths, preventing tangling and minimizing connections between logic and memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are stacked in a POP device to improve compactness, then the compactness and performance of electronic products are improved, but the wiring layout becomes complex leading to deteriorated routability and signal connection performance
Solution Approach 1:
The patent segments the connection interface into multiple sides of the package substrate. Connection pads are distributed along different side portions (first side portion, second side portion, third side portion, fourth side portion) rather than concentrated in one area. This segmentation allows signal routing to be divided into multiple independent paths, reducing wiring complexity and improving routability while maintaining compact stacked configuration.
Solution Approach 2:
The patent utilizes the lateral dimension of the package substrate by arranging connection pads along the perimeter sides rather than only in the central area. This dimensional redistribution of connection interfaces enables shorter and simpler wiring paths between stacked chips, resolving the routing complexity issue while preserving the compact vertical stacking architecture.
2Ease of operation
If wiring paths are reduced and simplified to prevent tangling, then routability is improved, but the connection layout requires precise side-by-side arrangement of chips
Solution Approach 1:
The patent employs preliminary alignment features including alignment marks and protrusion-recess structures that are pre-formed on the chips and package substrate. These features guide the precise side-by-side arrangement of chips during assembly, ensuring that connection pads on adjacent chips align correctly with corresponding connection pads on the substrate before wiring is performed. This preliminary positioning action simplifies the subsequent routing process while maintaining manufacturing precision.
Solution Approach 2:
The package substrate acts as an intermediary element with connection pads distributed along its sides. This intermediary structure provides standardized connection points that mediate between multiple chips arranged side by side. The substrate's pre-defined connection pad locations serve as reference points that guide chip placement and simplify wiring connections, balancing the need for precision with ease of routing.
3Speed
If connection wiring paths between interface portion and connection pads are minimized, then high-speed performance is achieved, but the interface layout becomes more constrained
Solution Approach 1:
The interface connection is segmented into multiple independent connection regions located at different sides of the package substrate. Each side portion (first, second, third, fourth side portions) can independently support connection pads for different signal groups. This segmentation allows minimization of wiring paths for each interface group while maintaining overall interface layout flexibility through the distributed arrangement of connection points around the substrate perimeter.
Data Source
AI summary
A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.