Stack-Type Memory Leakage Control Block
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Solution Overview
Problem
Stack-type semiconductor devices face increased charge leakage due to vertically stacked memory cells, which affects the control of these cells and requires new solutions to reduce leakage and ensure effective control.
Innovation Solution
A stack-type memory device is designed with a leakage control block interposed between the memory cell array and the peripheral circuit block, featuring selection switches with vertical channels made of single crystalline semiconductor material to selectively connect or disconnect memory cell strings from the peripheral circuit block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked to increase integration degree, then integration density is improved, but charge leakage increases
Solution Approach 1:
A leakage control block is introduced as an intermediary component between the memory cell array and the peripheral circuit block. This block includes selection switches that can be controlled to disconnect memory cell strings from the peripheral circuit, thereby preventing charge leakage from affecting the peripheral circuit while maintaining the vertical stacking structure for high integration density
2Object-generated harmful factors
If selection switches are added to control leakage, then charge leakage is reduced, but device complexity increases
Solution Approach 1:
The selection switches are implemented with vertical channels extending in the third direction (vertical dimension), rather than using conventional planar transistors. This vertical configuration allows the switches to be integrated into the stacked memory structure without proportionally increasing the footprint area, thereby reducing the overall device complexity despite adding leakage control functionality
Data Source
AI summary
A stack-type memory device may include a memory cell array, a peripheral circuit block and a leakage control block. The memory cell array may include at least one memory cell string. The memory cell string may include a plurality of memory cells vertically stacked. The peripheral circuit block may include circuits configured to control operations of the memory cells. The leakage control block may be arranged between the memory cell array and the peripheral circuit block. The leakage control block may include at least one selection switch. The selection switch may selectively connect the memory cell string with the peripheral circuit block and disconnect the memory cell string from the peripheral circuit block. The memory cell array, the leakage control block and the peripheral circuit block may be stacked in the vertical direction.