Stack-Type Semiconductor Package Pad Arrangement
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Solution Overview
Problem
The increasing demand for mobile devices with multiple functions, such as smartphones, leads to a need for integrating communication and media processors in a single package, resulting in complex wiring structures that decrease routability and increase the thickness of semiconductor packages due to the stacking of multiple semiconductor chips.
Innovation Solution
A stack-type semiconductor package design with a pad structure that includes a logic chip and multiple memory chips, where connection pads are strategically arranged to simplify the interconnection between chips, reducing signal path lengths and package thickness while maintaining efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked in a package to integrate communication and media processors, then the functionality and performance of the device are improved, but the wiring structure becomes complex and routability decreases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical wiring by stacking semiconductor chips in the thickness direction. Connection pads are arranged on different layers (first package substrate, second package substrate, and intermediate connection pads), enabling signals to travel vertically through the stack rather than horizontally across a complex planar layout. This dimensional change simplifies the wiring structure while maintaining high functionality integration.
Solution Approach 2:
The patent divides the integrated system into separate semiconductor chips (communication processor chip and media processor chip) that are stacked and independently packaged. Each chip maintains its own pad structure and wiring, which are then connected through standardized connection pads on the package substrates. This segmentation allows each chip to be optimized independently while simplifying the overall interconnection structure.
2Productivity
If multiple semiconductor chips are stacked in a package, then processing capacity is improved, but package thickness increases
Solution Approach 1:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within a compact package. The first semiconductor chip is mounted on the first package substrate, and the second semiconductor chip is mounted on the second package substrate, which is positioned above the first. Connection pads extend through intermediate layers, creating a nested arrangement that maximizes processing capacity within minimal thickness.
Solution Approach 2:
The patent utilizes the vertical dimension (thickness direction) for chip stacking and signal transmission. By arranging connection pads and wiring in the vertical direction rather than spreading them out horizontally, the package achieves high processing capacity with reduced lateral footprint and controlled thickness.
3Device complexity
If connection pads are arranged to simplify interconnection, then routability is improved, but signal path length may increase
Solution Approach 1:
The patent employs different connection pad arrangements for different signal types and different locations within the package. First DQ connection pads and first CA connection pads are positioned at specific locations on the first package substrate, while second DQ connection pads and second CA connection pads are positioned on the second package substrate. This localized optimization allows signals to take the most direct paths from their source to destination, balancing interconnection simplicity with minimal signal path length.
Data Source
AI summary
Provided is a stack-type semiconductor package comprising a first semiconductor package with a first package substrate and a logic chip mounted thereon, a second semiconductor package including a second package substrate disposed on the first semiconductor package and first and second memory chips stacked on the second package substrate, and connection pads disposed between the first and second package substrates to connect the first and second semiconductor packages electrically to each other. The first package substrate has first and second edges that are substantially perpendicular to each other. The first package substrate may include first DQ connection pads electrically connected to the first memory chip, and second DQ connection pads electrically connected to the second memory chip. The first DQ connection pads may be arranged adjacent to the first edge and the second DQ connection pads may be arranged adjacent to the second edge.