Stack-Type Semiconductor Package Recessed Lower Molding Layer
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Solution Overview
Problem
Current stack-type semiconductor packages face challenges in reducing thickness while maintaining high operation speed and low power consumption, as they often require longer signal transmission paths due to their structural design.
Innovation Solution
The proposed solution involves a stack-type semiconductor package design with a lower substrate and upper substrate configuration, where the upper chip structure projects into a recessed region of the lower molding layer, allowing for a reduced thickness by using a connection structure such as a single ball, multiple ball, spacer, or through electrode structure to connect the electronic parts, and incorporating a protection layer to cover the exposed wires and chip structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a conventional stack-type semiconductor package structure is used, then high capacity and reduced signal transmission path are achieved, but the package thickness cannot be sufficiently reduced
Solution Approach 1:
The upper chip structure is nested into the recessed region of the lower molding layer, allowing the upper substrate to be positioned closer to the lower chip. This nesting arrangement reduces the overall package thickness while maintaining the vertical stacking configuration that ensures short signal transmission paths between chips.
Solution Approach 2:
The invention introduces a vertical dimension optimization by creating a recessed region in the lower molding layer. This allows the upper chip assembly to extend downward into the recess, effectively utilizing the vertical space to reduce package thickness without compromising the horizontal layout needed for electrical connections.
2Speed
If the package thickness is reduced, then the signal transmission path is shortened, but the structural complexity increases due to recessed region and protection layers
Solution Approach 1:
The recessed region is formed in the lower molding layer before the upper chip structure is assembled. This preliminary preparation allows for easier and more precise placement of the upper chip, reducing assembly complexity. The protection layer is also pre-formed to cover exposed wires, simplifying the final assembly process while ensuring proper wire coverage.
Solution Approach 2:
The protection layer acts as an intermediary element that covers exposed wires and provides mechanical support. This mediator component simplifies the overall structure by consolidating wire protection and structural support functions into a single layer, reducing the need for additional complex protective structures.
3Length of moving object
If wire bonding structure is used to connect chips, then electrical connections are established, but the package thickness increases due to wire length
Solution Approach 1:
The electrical connection path is segmented into multiple components: connection structures (such as bumps or pads) on the chips, wires for interconnections, and the recessed region that accommodates these elements. This segmentation allows each component to be optimized independently, enabling shorter wires and reduced package thickness while maintaining proper electrical connections.
Data Source
AI summary
An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.